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DS250DF230: Request a Design review for DS250DF230

Part Number: DS250DF230

Hello

I attached design file.

Could you review a design for DS250DF230? (25G CDR)

Best regards.

  • Hi,

    I reviewed the schematic. My inputs below

    Checked and ok

    • VDD decoupling
    • 25MHz oscillator signal assumed for CAL_CLK_IN
    • ADDR pins strap option
    • SDA and SCL assumed to have adequate resistor pull-ups to 2.5V or 3.3V
    • EN_SMB -> 1KOhm pullup to VDD for normal operation in SMBus Slave Mode
    • READ_EN_N floating for normal operation in SMBus Slave Mode
    • ALL_DONE_N floating
    • INT_N floating
    • TEST pins floating

    Comment

    • The high-speed inputs and outputs do not appear to have external AC coupling caps implemented per TI recommendation 

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer