DP83822IF: COL pin internal pull-up/pull-down
Part Number: DP83822IF
My customer use DP83822I and found an issue. For bootstrap mode COL pin, customer use default mode -- MODE 4 , without external pull up or pull down. So based on below Table 10, the voltage of COL shall be high VDDIO . But customer measured the voltage of COL, and found during reset stage, the COL is High, but after reset de-assert, the voltage of COL become and keep low. So what's reason?
I do not see the images that you have tried to share. Can you please send the diagrams again?
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In reply to Cecilia Reyes:
The table 10 is the datasheet's. And the waveform is below. As you can see, when reset is de-asserted, the COL pin go to low. But from datasheet table 10, the mode 4 the COL shall be high VDDIO.
In reply to Garrick Dai:
Can you please share the register dump for this device? 0x0-0x1f As well as 0x467. I'd like to confirm the strap status of COL pin
Please check below table for reg value, in which record both reg data in abnormal and normal situation. Customer only record 0x00~0x1f. .
Garrick - Can you explain what normal and abnormal situation is?
Does that mean in normal situation COL pin stays high?
It looks like in abnormal situation there is no link between the devices is that because you have recorded the readings during reset?
I need register 0x467 because it will tell me the status of the strap pins.
No, COL pin behave same(high go to low after reset) for both normal and abnormal situation. The normal means the PHY can work normally after power on and the abnormal means the PHY disconnect. The issue now is, if config Mode 4, whether or not the COL behave(high go to low after reset) is ok and why. Thanks.
Hi Garrick - I will need to reach out to my team to understand the COL behavior after reset. I see that you have linked to a similar E2E thread. Let me get back to you by EOD tomorrow and understand the answer from the previous post.
Can you please also share reg 0x467 at your convenience?
We have confirmed in the lab in the past to understand the status of COL and it looks like the COL pin is internally pulled-up.
Just to confirm again, when you are checking this pin’s internal pull, there are no external pulls attached to this pin and you are holding the device in reset?
The device COL pin is left open, without any external pull up or pull down, because customer need config Mode 4. The issue is, COL pin will become from HIGH to LOW after reset (not during reset).
BTW, I checked datasheet 7.7 and found -- From reset state until the device latches the boot pins only takes 120ns +64ns for the device to switch into the HW function of the pin. So I am not sure if the COL pin only keep HIGH during reset time and T3 timing, after that, the COL pin become MII COL functional pin and change to LOW. Is this correct understanding or not?
Do you have another device or EVM you can test that confirms this theory? I am wondering if other devices are also affected and that you see the same phenomenon.
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