DP83822IF: DP83822 COL pin behave abnormal

Hi Garrick,

I do not see the images that you have tried to share. Can you please send the diagrams again?

Thanks,

Cecilia

The table 10 is the datasheet's. And the waveform is below. As you can see, when reset is de-asserted, the COL pin go to low. But from datasheet table 10, the mode 4 the COL shall be high VDDIO.

Can you please share the register dump for this device? 0x0-0x1f As well as 0x467. I'd like to confirm the strap status of COL pin

Thanks,

Cecilia

Please check below table for reg value, in which record both reg data in abnormal and normal situation. Customer only record 0x00~0x1f. .

Garrick - Can you explain what normal and abnormal situation is?

Does that mean in normal situation COL pin stays high?

It looks like in abnormal situation there is no link between the devices is that because you have recorded the readings during reset?

I need register 0x467 because it will tell me the status of the strap pins. 

Thanks

Cecilia

Hi Cecilia,

No, COL pin behave same(high go to low after reset) for both normal and abnormal situation. The normal means the PHY can work normally after power on and the abnormal means the PHY disconnect. The issue now is, if config Mode 4, whether or not the COL behave(high go to low after reset) is ok and why. Thanks.

Hi Garrick - I will need to reach out to my team to understand the COL behavior after reset. I see that you have linked to a similar E2E thread. Let me get back to you by EOD tomorrow and understand the answer from the previous post.

Can you please also share reg 0x467 at your convenience? 

Thanks,

Cecilia

Hi Garrick

We have confirmed in the lab in the past to understand the status of COL and it looks like the COL pin is internally pulled-up.

Just to confirm again, when you are checking this pin’s internal pull, there are no external pulls attached to this pin and you are holding the device in reset?

Thanks,

Cecilia

Hi Cecilia,

The device COL pin is left open, without any external pull up or pull down, because customer need config Mode 4. The issue is, COL pin will become from HIGH to LOW after reset (not during reset).

BTW, I checked datasheet 7.7 and found  -- From reset state until the device latches the boot pins only takes 120ns +64ns for the device to switch into the HW function of the pin. So I am not sure if the COL pin only keep HIGH during reset time and T3 timing, after that, the COL pin become MII COL functional pin and change to LOW. Is this correct understanding or not?

Hi Garrick,

Do you have another device or EVM you can test that confirms this theory? I am wondering if other devices are also affected and that you see the same phenomenon. 

Thanks,

Cecilia

I have not EVM on hand. My customer have tested several boards and got same issue. Could you please check and confirm this issue? 

Hi Garrick

I confirmed with an EVM that the COL is internally pulled up. My apologies if you mentioned this previously but is COL connected to anything else? I know you said that you left the straps open but is the COL connected to a CPU that could be driving this pin low? 

Thanks,

Cecilia

Hi Cecilia,

I know COL has internal pull up. I want to double confirm below. Whether or not, the COL pin only behave as strap boot pin during reset? as reset and after T3 time, the COL pin change back to normal HW function of I/O.

From reset state until the device latches the boot pins only takes 120ns +64ns for the device to switch into the HW function of the pin, here see section 7.7 in the datasheet. Then by HW function of COL pin,  it has below description in spec --

COL pin description in datasheet--

"Collision Detect: For Full-Duplex mode, this pin is always LOW. In Half-Duplex mode, this pin is asserted HIGH only when both transmit and receive media are non-idle.
Unused in RMII Mode "

Hi Garrick,

I can confirm on our EVM this week. Please allow me until the middle of the week to confirm in lab.

Thanks,

Cecilia

HI Cecilia,

Why we cannot confirm the pin behave from theory first, but just test on EVM? If anyone from BU team can check this?  It already past one more week when just ask for the question...

Hi Garrick my interpretation was that I thought you wanted the engineers to confirm in our lab. 

However just based on the theory, during Reset as mentioned in the datasheet should be pulled up. You are correct it behaves as the bootstrap at reset. Once reset is completed COL should stay low. 

Hi Cecilia,

Please check and confirm the issue in our lab. The phenomenon of waveform looks strange compared to theory. As below, at the moment reset begin to de-assert, the COL pin go to LOW immediately. But from theory, the COL pin shall be pull LOW after reset de-assert plus T3 time.

Hi Garrick based on the capture I do believe that the PHY is behaving as expected as it could be reaching the threshold of the RESET to trigger the COL to go low. 

Can you please share the rise and fall time of these as well as a zoomed in scope shot of the time that RESET is increasing to when COL goes low. I don't see what the time scale is for this so it is hard for me to understand the measurements. 

It would be helpful to see the delta of time from RST starting to increasing to when COL switches low