DS90UB941AS-Q1: Unstable link with forward channel dsi + back channel i2c and GPIO

Hi Manoj,

Just to clarify a few things:

The flickering only happens when I2C is read from 941 to the 948 and when there is an interrupt from the 948 to the 941? 

Does this flickering stop after the I2C is read? 

when you say "link pin" do you mean lock pin?

What is the Pclk of the video being sent?

Regards,

Michael W.

Hello Michael, 

Here is the flow, 

1.Interrupt from 948--> 941--> soc

2. i2c read request from soc--> 941--> 948 --> slave device(and requested data send back to soc). Along with video sometimes i2c read requests will be failed. And all the time's video flickering will be observed.

When there is no video data to 941, interrupt, i2c read/write will be 100% success. 

Yes, video flickering will stop after the above flow.

yes, it is 948 lock pin.

Pclk is 71.9Mhz.

Regards,

Manoj

Hi Manoj,

When you are using the pattern generator of the 941 are you using the 941 internal clock or the DSI clock? your DSI clock is in continuous mode on the SOC correct? 

If the video data and I2C reads fail like you have described the lock pin of the 948 should have dropped low, how are you monitoring the lock pin?

Regards,

Michael W.

Hi Michael, 

Pattern generator is working without any issue on both internal clock and DSI clock..

65h(PGCFG_PGCFG_P1 Register) --> 0x05  Color bar will be always ON.

65h --> 0x01 Color bar will be ON when valid DSI clock input.

DSI clock is set to HS clock always.

Normally Lock pin will be high and with interrupt, i2c read/write lock pin will go low for few ms(we have test point to check), at the same time we see flickering on display.

Regards,

Manoj

Hi Manoj,

What interrupt is present when the issue is happening? How often does this issue occur? Is the register dump you posted during when the issue is happening? if not can you capture a register dump when the issue is happening?

Regards

Michael W.

Hi Michael, 

GPIO_0 or GPIO_1 will go low from high on interrupt(triggered by slave device connected to 948),

Issue is seen every time with interrupts and flowed by i2c read/write.  Register dump is captured just after the issue.

Regards,

Manoj 

Hello Manoj,

Due to the US public holiday our team members are our of office but we will follow up with you next week on Monday to continue this thread

Best Regards,

Casey

Hi Manoj,

Can you disable any interrupts and I2C read or writes going to or from the SOC to the 941A once the link is up? Will the display flicker then?

Regards,

Michael W.

Hi Michael, 

If we disable the interrupts and i2c read/write, the frequency of flickering is very less.  and it flickers every time with interrupts and i2c. 

Regards,

Manoj

Hi Manoj,

This issue is seeming to be a signal integrity issue. Can you follow the 941AS and 948's datasheet and run BIST to confirm it is a signal integrity issue?

Regards,

Michael W.

Hi Michael, 

We see some error on GENERAL_STS(0x27) DSI_ERROR and DES_ERROR, what does it mean?  can we clear this bit?

BIST 

1. enabling BIST on 948 0x24 --> 0x01 (941 0x14 becomes 0x01 automaticaly) lock and pass line goes to LOW.

2. enabling BIST on 941 0x14 --> 0x03 or 0x01 lock and pass line goes to LOW

Is the BIST configuration is correct?

Regards,

Manoj

Hi  Michael, 

above BIST configuration is working with the active DSI input clock to 941. 

With this, we could see PASS pin is in high and it goes low for few us. So the issue is on dsi input clock or SerDes link?

How can we check this with internal clock? setting 0x14 to 0x03 on 941 is not working.

Regards,

Manoj

Hi Manoj,

to enable BIST all you need to do is write 948 0x24 --> 0x01. 

It seems to be that your issue is caused by a signal integrity issue. Can you accept my friend request and send me the layout for your board to verify that your layout is correct.

Regards,

Michael W.

Hi Michael, 

Setting 948 0x24 --> 0x03 or 0x07, We see PASS line is always HIGH. What does it mean?

PASS line is going low when we set 948 0x24 --> 0x01.

Regards,

Manoj

Hi Manoj,

It could also be pointing to signal integrity issues on the DSI clock lane or the SOC's DSI is not within our requirements which SOC are you using?

Regards,

Michael W.

Hi Manoj,

Any updates?

Regards,

Michael W.

Hi Michael, 

Deserializer board is already reviewed by TI. 

We will check and come back on DSI input signals. We are using Snapdragon chipset, do you have any reference or list of DSI input requirements on 941? 

Regards,

Manoj

Hi Manoj,
The DSI Requirements are in the "AC Electrical Characteristics" section of the datasheet on page 16 and 17.

Regards,

Michael W.

Hi Prasad,

Were you able to measure the signal on the DSI lines?

Regards,

Michael W.