DS90UB933-Q1： DS90UB933-Q1：NO OUT PUT

Hello,

Can you plot a block diagram showing how is your system working, and which I2C addresses/ Mode Pin settings?

Also would be very helpful if you can share a register dump from the 960 for the correct RX port.

Hello,

Thanks for sharing this.

Can you give more details, in which type of error or error message are you getting?

Regarding this issue, I found the latest datasheet. GP02 added a 47K pull-down resistor to ground (normally this PIN is not used); the current test time from VDD to PDB is 2ms; there will be a problem that the 933 will not output normally;

The power-on time of PDB has been tested to be 2ms; but there is still a probability of non-startup; is there any other areas that need improvement besides these two locations?

When there is a problem, read the registers of 933 through 960 as follows:

/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x00,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x01,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x02,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x03,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x04,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x05,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x06,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x07,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x08,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x09,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0a,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0b,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0c,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0d,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0e,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4l-subdev9 = 3, data[2] = 0x0f,0x00, 2) failed
VIDIOC_MSM_SENSOR_CFG: failed: Invalid argument
/data/ccidbgr: i2c_write(/dev/v4

It looks like you do not have communication between the SER and DES. Do you have LOCK at this time or also no LOCK?

Is a digital reseting the 933 heals the problem?

there is no lock signal  when ser and des have no communication.

how to digital reset ser(933)?pls give a brief explanation

Digital resetting the 933 by locally writing 0x02 into register 0x01.

thank you for your support:
According to the requirements of DATASHEET, I will reset the 0X27 register using external I2C, and the screen will return to normal; (At this time, I have grounded the GPO using 47K resistors according to the requirements, and the PDB power-up time is about 2ms); some documents have seen this before The timing is to prevent the chip from entering the TI internal test mode when it is powered on; I have the following questions:
1. Does the timing modification not completely solve the problem of occasional non-startup at power-on and power-off, should the register 0X27 be reset at the same time?
2. What are the conditions for the chip to enter TI internal testing? I will check if there is still a problem with our design;
3. The chip information indicates that when the problem occurs, configuring 0X27 can solve the problem, but (only for local control) can not use the remote; I think if there is an ISP chip inside the camera can solve the problem perfectly; if there is no ISP inside the product only How to deal with the problem of power supply, sensor, and serializer?

Hello,

1) You need to reset 0x27 only if the timing requirement for T3 is not maintained.

2) If GPIO2 was for some reasons pulled high before or at the same time when PDB is released.

3) If you do not have an ISP or uC in the camera, then you need to make sure during the design phase that T3 (VDD_n to PDB) is greater than 0ms and smaller that 16ms. This can be achieved using a 10Kohm + 10uF. 

I have modified the relevant timing according to the requirements. After testing, the PDB startup time is about 2ms; I still need to reset the register to return to normal; what is the reason?

Hello,
can you send a screen shot showing the Oscilliscope measurements of VDDIO, VDD_n, PDB and GPO2 at the same time? i.e. similar plot to figure 28.

The picture above is the timing data of my test

Thanks for sharing this!

Can you please send me two register dumps from the 960, one time for a good case and the system working normally, and the other dump once you do not have output from SER?

Also is it possible to share the schematic from your SER and from the DES?

Sorry we only have the 933 drawing; when there is a problem, the 960 side cannot read any information of 933; I need to add the pull-down resistance to GPO2 to find the latest information, and I still have a fault after modification according to the requirements. Only through the internal software. Set to 0X27 to return to normal