This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

[FAQ] SN65DSI84: How to configure the SN65DSI84 and SN65DSI85 for single channel DSI to dual channel LVDS

Mastermind 27280 points

Replies: 6

Views: 170

Part Number: SN65DSI84

This thread will provide a step-by-step guide on configuring the SN65DSI84 and SN65DSI85 for single DSI input to dual LVDS output operation.

Materials needed:

1.DSI-Tuner (you can download the latest version here: https://tidrive.ext.ti.com/u/5B25JYQduSH2Hbkl/DSI%20Tuner%202.1.zip?l

2.Display datasheet (this example will use the attached G133HAN01.0 display datasheet):G133HAN01.0_Datasheet_01.pdf

http://www.apollodisplays.com/g133han01-0/

  • Step 1:

    Download, install, and open the DSI-Tuner. Select the SN65DSI84 or SN65DSI85 as the target device. In the “Panel Inputs” tab, change the “LVDS Mode” to Dual:

    Step 2:

    Enter the resolution of the display in the “Resolution” inputs. The G133HAN01.0 display is 1920x1080:

    The “LVDS_HActive” and “LVDS_VActive” inputs will be auto-populated – do not change these values.

  • In reply to I.K. Anyiam:

    Step 3:


    Fill out the pixel and line inputs. This information should be available in a table in the datasheet like below:

    It is important to note here that all of the horizontal timing parameters have been divided by 2. For example, the datasheet shows that the number of active horizontal pixels is 960. This is because the timing information is for one channel or one half, of the display.

    Think of a display vertically cut in half into two separate displays – the amount of vertical lines stays the same but all of the horizontal parameters (frequency, active pixels, blanking pixels) will also be cut in half.

    If your display datasheet does not show the horizontal parameters divided by 2 (you can tell by seeing whether or not the horizontal active pixels have been halved), then you will need to ensure to divide them by 2 by yourself.

    If your display datasheet only shows the total blanking and not HPW, HBP, HFP, VPW, VBP, and VFP individually, then you simply need to make sure that the sum of HPW, HBP, and HFP add up to the total horizontal blanking, and that VPW, VBP, and VFP add up to the total vertical blanking:

  • In reply to I.K. Anyiam:

    Step 4:

    Check the data mapping format in your display datasheet and match it up with the SN65DSI84/85 supported format:

    This matches Format 1:

    Select this for both Channel A and Channel B, and change the Bits Per Pixel to 24bpp:

    Step 5:

    Check the polarity of Data Enable, HSYNC, and VSYNC from the timing diagram in your display datasheet:

    Like the above, most datasheets operate in DE mode only so the polarity of HSYNC/VSYNC does not matter here. From the timing diagram, you can see that every time there’s active pixel data, DE is high. This means the DE polarity is positive:

    If your display cares about the polarity of HYSNC/VSYNC, then the timing diagram will show the polarity by having HSYNC/VSYNC go either high or low each time active pixel data is about to start.

     

  • In reply to I.K. Anyiam:

    Step 6:

    You can now switch over to the “DSI_Inputs” tab. Make sure the “DSI Ch Mode” is Single.

    Fill out the pixel and line information. Since this is single DSI to dual LVDS, the horizontal DSI timing parameters need to be double that of each channel in the horizontal timing parameters from the “Panel Inputs” tab (refer to step 3).

    The vertical timing parameters need to be the same as the inputs in the “Panel Inputs” tab.

    Step 7:

    Verify the #of DSI data lanes and video mode. This example uses all 4 DSI data lanes and RGB888:

  • In reply to I.K. Anyiam:

    Step 8:

    Fill out the CLK inputs. The LVDS CLK frequency should be given in the timing table in the display datasheet (refer to step 3). For this display it is 70.6 MHz.

    You can use either the DSI CLK input or an external reference clock to source the LVDS CLK. This example uses the DSI CLK to source the LVDS CLK.

    To determine the DSI CLK frequency, use the following equation:

    For this example, this works out to be 423.6 MHz:


    Make sure to also select the correct divisor value to get the desired LVDS CLK frequency.

    Step 9:

    Click the calculator icon in the bottom right corner to get to the “Outputs” tab. Note that the “Line Time” on the LVDS output and the “Data burst time” on the DSI input should be almost exactly the same number:

  • In reply to I.K. Anyiam:

    Step 10:

    Press ctrl+e to export the .dsi file so that you can import it later if you want to make changes (press ctrl+i to import a .dsi file).

    Press “Generate CSR List” in the upper left corner:

    Press “Export to Text File” to generate the register settings in a text file:

    You can use the register settings in this text file to configure the SN65DSI84 or SN65DSI85. Note that the PLL is not enabled by default in these settings since it must be enabled in accordance with the initialization sequence in the datasheet.

    Additionally, it is critical that the output from your DSI source matches exactly with the settings you put into the DSI-Tuner (DSI CLK frequency, active pixels, blanking pixels, etc) for correct operation.

    If you encounter issues after going through this FAQ, please reference this FAQ for debug tips: https://e2e.ti.com/support/interface/f/138/t/852871

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.