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DS110DF410EVM: Cannot access board across USB

Part Number: DS110DF410EVM
Other Parts Discussed in Thread: USB2ANY, DS110DF410

hi

i have dowbloaded software, and update for this board,

powered up of 3.3 volts, currently drawing 80 ma

2V5 is up

2v5 led is red

SMBUS LED is green

how-ever when i plug in USB cable, driver is installed, but GUI reports on USB2ANY devices found

how do i communicate with board ?

Davey

  • Hi,

    As described the latest DS1xxDF410 EVM user's guide (refer to Section 2,2), TI's latest SigCon Architect GUI software requires a USB2ANY interface to the retimer I2C pins.

    https://www.ti.com/lit/ug/snlu126c/snlu126c.pdf

    As the older DS110DF410 EVM  does not implement USB2ANY circuitry onboard, you will need to separately order a USB2ANY dongle. See TI link below.

    www.ti.com/.../USB2ANY

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • This is very disappointing on an $800 board that when i look at it and schematics it has the micro the converts from USB to I2C that is exactly what the pod has

    can you please supply me loan of POD ASAP

    we are planning on using the retimer as a PRBS patteren generator. we will not be having an input data stream, but will provide a clock to inputs at 1/16 of line rate

    can you advise what registers i need to modify to acheive this

    Davey

  • Hi Dave,

    I personally do not have a USB2ANY unit I can loan you. Please work with our sales representative Dave Anderson on this order request.

    If you are providing divide by 16 clock pattern input data, the following channel register settings apply.

    REG       Value    Mask     Comment

    0C          00           08           // Turn Single Bit Limit Check Off

    18           00           70           //Select Divide by 1

    9             04           04           //Enable divsel override

    30           00           0F           //Disable PRBS Gen

    1E           00           E0           //Select PRBS Gen

    09           20           20           //Enable Mux Override

    1E           80           E0           //Select PRBS Gen

    1E           10           10           //Powerup PRBS Gen Analog

    79           20           60           //Enable PRBS generator and disable PRBS checker

    30           0A          0F           //Powerup PRBS Clk and select PRBS31

    Cordially,

    Rodrigo Natal

     

  • Good morning

    Thank-you for getting back to me so Quickly

    I have a few questions, relating to register sequence provided

     

    Should we be doing a check to make sure that we have signal lock before setting up PRBS?

    First operation, why do we need to Turn Single Bit Limit Check Off ?

    Should line 2 & 3 be swapped as per data sheet section 8.5.11 paragraph 2 ?

    After we have changed divide to 1, should DIVSEL overridde be changed back to default value of 0 ? or left at 1 ?

    With ip data a 644.53125Mhz Clock, I assumed with divide set to 1, the the recovered clock is 644.53125Mhz and will be used to clock PRBS. Does this mean that output with have line rate of 10.3125G ?

    Line 4 why do we disable PRBS ?

    Register 0x79is not documented, please provide details

    Do I need to set bit 5 of register 0D as per programming guide section 3.22 ?

     

    Analog questions

    Does all RX inputs have internal 100 ohm termination?

    While running PRBS in set up about do you have and indication of how much power will be used, just want to size our power supply. Power is stated as 720mw does this include PRBS power, Guess i can prove this out on eval board.

    Thank-you Davey

  • Hi Davey. See my inputs below to the questions.

     

    Should we be doing a check to make sure that we have signal lock before setting up PRBS?

    That is a good idea.

    First operation, why do we need to Turn Single Bit Limit Check Off ?

    If you are using low speed clock input signal there may not be enough data transitions to meet the SBT check criteria. Turning SBT off allows you to achieve CDR lock for low transition density input data

    Should line 2 & 3 be swapped as per data sheet section 8.5.11 paragraph 2 ?

    I don't think it should make a difference

    After we have changed divide to 1, should DIVSEL overridde be changed back to default value of 0 ? or left at 1 ?

    Left at 1

    With ip data a 644.53125Mhz Clock, I assumed with divide set to 1, the the recovered clock is 644.53125Mhz and will be used to clock PRBS. Does this mean that output with have line rate of 10.3125G ?

    Yes the output data rate will be 10.3125Gbps. When you force divider of 1 the CDR treats input data as 10.3125G. it assumes 8T input pattern (i.e. eight ones and eight zeros.)

    Line 4 why do we disable PRBS ?

    This ensures clearing of any previous configuration

    Register 0x79is not documented, please provide details

    I just realized I mistakenly provided the PRBS generator enable sequence from 25G version of retimer. My apologies. The correct sequence is the one in the 10G programming guide. See below.

    Table 35. Register Writes to Enable PRBS Generator

     

    STEP

    SHARED/CHANNEL REGISTER SET

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

    COMMENT

    1

    Channel

    Write

    09

    20

    20

    Override Output Multiplexer

    Select.

    2

    Channel

    Write

    1E

    80

    E0

    Turn on serializer (ser_en=1).

    3

    Channel

    Write

    1E

    10

    10

    Power-up PRBS Generator.

    4

    Channel

    Write

    30

    00

    08

    Reset PRBS Clock.

    5

    Channel

    Write

    30

    08

    08

    Power-up PRBS Clock.

    6

    Channel

    Write

    30

    00

    02

    03

    Select PRBS9 pattern. Select PRBS31 pattern.

    7

    Channel

    Write

    0D

    20

    20

    Enable PRBS Clock triggering on Div/Clock so that the eye diagram is viewable. Disabling results in Pattern Cycle triggering.

    Do I need to set bit 5 of register 0D as per programming guide section 3.22 ?

    Yes.

    Does all RX inputs have internal 100 ohm termination?

    Yes.

     

    While running PRBS in set up about do you have and indication of how much power will be used, just want to size our power supply. Power is stated as 720mw does this include PRBS power, Guess i can prove this out on eval board

    No, PRBS generator is not included. Enabling generator would add around ~200mW of power consumption per channel.