Hi Team,
May I ask which time duration is for DP83822I to read the bootstrap pin status after reset? It seems to be T3 latch-in time in datasheet Figure 2.
But when our customer trying to test this timing, they found that bootstrap pin will be held by DP83822I itself(indicate hardware latch-in is over) before RESET rise to middle point. Please refer to the waveform below.(CH1(yellow): RESET, CH2(blue): RX_D0, CH3(purple):CRS).
We have a rising time for RESET mainly because the capacitor at the RESET pin.
If we remove C453, we will see a higher dv/dt at RESET, but bootstrap pin will still be held low before RESET rise to middle point.
Can we confirm that the T3 is the duration for DP83822I to read the bootstrap pin status after reset? If so, which start point we should take(from which RESET pin voltage level/threshold)? And why bootstrap pin will be held low before RESET rise to middle point which is not the same as Figure 2?
Thanks.
Best Regards,
Livia
