XIO2001: Power-down Sequence when PCIR = 3.3V

Darren,

The PCIR voltage could back drive the VDD/VDDA_33 via ESD clamps, thus the recommendation in the datasheet.

I don't have a record of why the EVM does not follow the datasheet recommendation. I'm assuming that powering down PCIR and VDD/VDDA_33 almost simultaneously is probably acceptable, so no effort was made to align the EVM design with the datasheet recommendation.

Regards,
Davor

Hi Davor,

I really appreciate your help, thanks.

You said the reason for the recommendation for the sequence is due to the possibility of back-driving the ESD clamps.

In the case where someone wants to run:
- VDDA_33(XVDDA_3.3V in EVM) and
- PCIR(XPCI_VIO_1 and XPCI_VIO_2 in EVM) from the same supply (as in the EVM),
it should be safe to say that a similar design should be acceptable...?

Reasons:

- The 1kΩ and 0.1uF will cause the PCIR pin voltage to rise slower than VDDA_33, but still within the allowable range...?
- On power-down, where VDDA_33 goes to 0V, the capacitance on PCIR will keep the pin at 3.3V.
- But the 1kΩ resistor limits current through the ESD clamp (worst case ~ 3mA) for a very short time (0.1uF --> 1kΩ time constant)

In this case, there should be no damage to the device...right?

As you already mentioned:
"I'm assuming that powering down PCIR and VDD/VDDA_33 almost simultaneously is probably acceptable, "
so I am preparing to tell the customer that if they want to power them from the same rails, based on the design shown in the EVM, it should be acceptable.

Does the above thought process sound about right? Or is there another concern for an issue if PCIR > VDDA_33 for "too long"?

Thanks,

Darren