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Part Number: DS90UB936-Q1
My customer is going to use 24MHz reference clock instead of 25MHz crystal.
I know the forward channel data rate and CSI2 output are affected this slower reference clock and, the datasheet 7.4.4 REFCLK section describes "back channel rate, I2C timers, CSI-2 datarate, FrameSync signal parameters, and other timing critical internal circuitry" are works on the REFCLK but need more detail.
Could you list up "ALL" parameters which is affected from using 24MHz clock instead of 25MHz for example GPIO maximum frequency, AEQ relock time, I2C watchdog and high/low time or so?
The following parameters are affected by the REFCLK frequency:
High speed transmission: Data bit rate and DDR clock frequency (See page 14)
Bidirectional Control Channel: Data rate (See page 14)
Framesync: Scale high and low periods to 24 MHz (Page 47)
I2C High and Low times: Unit size of 40 ns assumes clock frequency of 25 MHz. With slower clock frequency of 24MHz, unit size will be scaled by a factor of 25/24, so 41.6 ns. Perform calculations accordingly. (Table 30 and 29)
AEQ relock time: The recommended value of 2.62 ms at 25 MHz allows 65500 cycles before relock. With a 24 MHz clock, 65500 cycles takes 2.72 ms. The closest value is 2.62, so the default should be fine. If you want to build in extra precaution, go next length of time up to 5.24 ms. (Section 22.214.171.124.3 and Table 159)
GPIO: Maximum sampling frequency is set to 4 * REFCLK for one linked forward channel GPIO. Maximum forward frequency is REFCLK (Table 9)
CSI TX Data rate per lane (Table 13) , ensure driver is programmed to receive at the correct rate (1536 Mbps at CSI_PLL_CTL value of 0x00)
This will affect, in turn, the Unit Interval (UI) CSI clock.
CSI-2 timing: t_CLK-POST, t_CLK_PRE, t_D-TERM-EN, t_EOT, t_HS-PREPARE, t_HS-PREPARE+t_HS-ZERO, t_HS-SETTLE, t_HS-SKIP (page 17, function of FPD Link UI) see figure 5 for visual representation
The serializer clock source determines the PCLK frequency and therefore the unit interval. This in turn determines many timing parameters for the 936. If operating in synchronous mode, the clock source is tied to the REFCLK, and changing the reference clock will affect the following parameters:
FPD-Link line rate = 160 * REFCLK
FPD3_PCLK = 4* REFCLK
Back channel rate = 2 * REFCLK (section 7.4.1)
FPD-Link Unit interval (UI) = 1/(PCLK_Freq * 40) (Table 6)
Back channel output eye width
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In reply to Carrie Kemmet:
Thank you for detailed explanation.
Sorry, I forgot to say but, my customer is going to use non-synchronous external clock mode. So forward channel include forward channel GPIO will not be affected. is it correct?
How about below parameters?
back channel GPIO
FV_MIN_TIME(there is a case Ser is 913A in customer's system)
I2C_SDA_HOLD, SDA_OUTPUT_SETUP time
In reply to Atsushi Hirai:
In non-synchronous clocking mode, FPD-Link line rate is determined by f_CLKIN. The forward channel GPIO data rate is directly affected by the FPD-Link line rate, so the REFCLK doesn't impact it in this case
Back channel rate should be set to 10 Mbps in non-synchronous mode. (Bits 2:0 of Register 0x58 to 010)
FV_MIN_TIME is affected by by FPD-Link frequency, which is not affected by REFCLK in non-sync mode.
BCC_Watchdog units scale by a factor of 25/24, so calculate according to units of 2.083 ms.
I2C_SDA_HOLD units also scale by factor of 25/24 to be 41.67 ns and SDA_OUTPUT_SETUP time values will also be scaled by 25/24.
FREQ_STABLE_THR values will also be scaled by 25/24.
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