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DS90UB960-Q1: 4 cameras cannot be turned on at the same time occasionally

Part Number: DS90UB960-Q1

hi teams:

we are using the 960+935+4 sensors.The sensor output is the same pixel  1920*1080.

we use 960 two ports output data to  two csi2 of cpu.

sensorA----------|   -------------960 csi2 port 0

sensorB----------|

sensorC----------|--------------960 csi2 port 1

sensorD----------|

4 sensors can be opened separatly, but can not be open at the same time occasionally.

when we using the 960+933+4 sensors, and the same pixel, there is no such phenomenon,

the 960 reg configuration is following, Are there any other inaccuracies? Please look at this problem for me, Thanks.

//"*** set RX0 VC=0 enable ***"
        ti960_write_reg(client, 0x4c, 0x01);
        //BCC_CONFIG Rx port access and 50Mbps
        ti960_write_reg(client, 0x58, 0x5e);
        //SER_ALIAS_ID Register setting
        ti960_write_reg(client, 0x5c, 0x30);
        //Remoute i2c slave addr
        ti960_write_reg(client, 0x5d, 0xda);
        //SLAVE_ALIAS_ID0
        ti960_write_reg(client, 0x65, 0xba);
        ti960_write_reg(client, 0xb0, 0x1c);
        //VC and DT set
        ti960_write_reg(client, 0x70, 0x1e);
        ti960_write_reg(client, 0x72, 0x00);
        msleep(5);

        //"*** RX1 VC=1 ***"
        ti960_write_reg(client, 0x4c, 0x12);
        ti960_write_reg(client, 0x58, 0x5e);
        ti960_write_reg(client, 0x5c, 0x32);
        ti960_write_reg(client, 0x5d, 0xda);
        ti960_write_reg(client, 0x65, 0xbc);
        ti960_write_reg(client, 0xb0, 0x1c);
        ti960_write_reg(client, 0x70, 0x5e);
        ti960_write_reg(client, 0x72, 0x55);
        msleep(5);
        //"*** RX1 VC=2 ***"
        ti960_write_reg(client, 0x4c, 0x24);
        ti960_write_reg(client, 0x58, 0x5e);
        ti960_write_reg(client, 0x5c, 0x40);
        ti960_write_reg(client, 0x5d, 0xda);
        ti960_write_reg(client, 0x65, 0xbe);
        ti960_write_reg(client, 0xb0, 0x1c);
        ti960_write_reg(client, 0x70, 0x9e);
        ti960_write_reg(client, 0x72, 0xAA);
        msleep(5);

        //"*** RX1 VC=3 ***"
        ti960_write_reg(client, 0x4c, 0x38);
        ti960_write_reg(client, 0x58, 0x5e);
        ti960_write_reg(client, 0x5c, 0x42);
        ti960_write_reg(client, 0x5d, 0xda);
        ti960_write_reg(client, 0x65, 0xc0);
        ti960_write_reg(client, 0xb0, 0x1c);
        ti960_write_reg(client, 0x70, 0xde);
        ti960_write_reg(client, 0x72, 0xff);
        msleep(5);

        //"CSI_PORT_SEL"
        ti960_write_reg(client, 0x32, 0x01);
        //"CSI_EN"
        ti960_write_reg(client, 0x33, 0x03);
        //"CSI_PORT_SEL"
        ti960_write_reg(client, 0x32, 0x13);
        //"CSI_EN"
        ti960_write_reg(client, 0x33, 0x03);
        //"CSI_PORT_SEL"
        ti960_write_reg(client, 0x20, 0xFC);
        ti960_write_reg(client, 0x20, 0x0C);