TLK10034: I have one of 4 ports that are accumulating data errors during BER testing.

I have a PCB design where 4 - TLK10034's are implemented. This effectively produces 16 channels on my PCB. The LS side of the device uses the XAUI interface. The HS side feeds a 10G optical transceiver. For 14 out of the 16 channels, the BER testing looks perfect (for 1 terabyte or more of data transfer there are no errors). For purposes of discussion I will refer to the different TLK's by letters (A, B, C and D). On TLK's B and C, these perform with no issues during BER testing. For TLK A 3 of the 4 ports perform with no issues during BER. One channel (Channel 2) will do an ethernet ping test with no problems (no packet loss when run for 1 minute or more). However, during BER testing, we are getting traffic errors that seem to be somewhat erratic (sometimes it will run well for awhile and then randomly produce errors and so on). We have a similar situation on TLK D. On the same channel (Channel 2) we see the same kinds of BER errors. The other 14 channels seem to run perfectly. We have run loopback tests where the loopback was done internally on the LS and HS side. The problem appears to be with the HS side since running the loopback internally or externally on the LS side produces the same results. We have inspected the physical aspects of the nets involved. The connection between the TLK A channel 2 HS port to the optical transceiver has been verified in both schematic and gerber data. The length of the differential net is approx. 1600mils which is comparable or even shorter than some of the channels that have no issues. For our configuration, we have the following register overrides from default...

Device Address Register Address Default Value Required Value Notes:
0x07 0x0000 0x3000 0x2000 Bit 12 changed from '1' to '0'
0x01 0x0096 0x0002 0x0000 Bit 1 changed from '1' to '0'
0x1E 0x000E 0x0000 0x000E Bits 1,2,3 changed from '0' to '1' to initiate a datapath reset
0x1E 0x0003 0x5848
0x1E 0x0004 0x5550

The 1st turns of autonegotiation which we need since we are connecting to an optical transceiver.
The second turns of KR_training which we also need due to the devices we are connecting to.
The third does a datapath reset which is required by the second item.
The 4th and 5th are specific values that we determined by trial and error to tune the channels for best performance.

The above, same register updates are performed for each of the 4 channels on the TLK10034. The values for each channel are identical.

We are currently changing the registers via an attached USB dongle that interfaces with the TLK10034 GUI. Based on the above changes, we are able to get 14 of the 16 channels working with no issues. One thing that we did notice is that adding some delay after the datapath reset appeared to determine how solid and repeatable the results were.

All this being said, we need assistance with debugging the final two channels on this PCB. As I mentioned, we have gone through the physical connections (there appears to be no issues). We have done tuning to improve the performance of the channels (this worked for 14 of the 16 channels, tuning will not make the remaining 2 channels better).

Some things that would help...

Is there a proper sequence for implementing the above register updates that we should follow? (i.e. does the sequence of events matter, should we be doing other resets while implementing the above register changes, should delays be inserted into the above sequence, etc...). Please advise.

As far as debugging the port with an issue, is there a procedure for stepping through settings to better understand the issue and pin point where we should be looking?

We need to resolve this issue. We have been trying various things over the past several weeks and we have not been able to pin point the issue.

Please take a look and get back to me ASAP. If you need further information please let me know what you need.

Thank you,
Mike Nycz