Other Parts Discussed in Thread: DP83869
Hello.
- DP83869HM has ANA_RGMII_DLL_CTRL Register (Address = 0x86). I don't understand these descriptions about TX and RX delays:
Steps of 250ps, affects the CLK_90 output. b[3],b[2],b[1],b[0], shift, mode 0, 1, 1, 1, 2.0ns, Shift (*) - default 0, 1, 0, 1, 1.5ns, Shift 0, 0, 1, 1, 1.0ns, Shift 0, 0, 0, 1, 0.5ns, Shift 1, 1, 1, 1, 0ns, Align (**) 1, 1, 0, 1, 3.5ns, Shift 1, 0, 1, 1, 3.0ns, Shift 1, 0, 0, 1, 2.5ns, Shift please note - the actual delay is also effected by the shift mode in reg 0x32.
There are several marks (* and **), but I can't find the descriptions of these marks. Also, I don't understand why does this description have information about align mode?
The item 9.4.4.2 1000-Mbps Mode Timing:
In Aligned mode, no clock skew is introduced.
I have compared this description about TX and RX DP83869HM RGMII delays with DP83867 RGMII delays. DP83867 datasheet has more undestandeable description:
1111:4.00ns 1110:3.75ns 1101:3.50ns 1100:3.25ns 1011:3.00ns 1010:2.75ns 1001:2.50ns 1000:2.25ns 0111:2.00ns 0110:1.75ns 0101:1.50ns 0100:1.25ns 0011:1.00ns 0010:0.75ns 0001:0.50ns 0000:0.25ns
Please, explain to me how do DP83869HM TX and RX delays work?
- I have checked, that RGMII_CTRL has different descriptions in DP83869HM and DP83867.
DP83869HM, RGMII_CTRL Register (Address = 0x32), RGMII_RX_CLK_DELAY bit
0x0 = RGMII receive clock is shifted with respect to receive data.
0x1 = RGMII transmit clock is aligned with respect to receive data.
DP83867, RGMII_CTRL Register (Address = 0x32), RGMII_RX_CLK_DELAY bit
1 = RGMII receive clock is shifted relative to receive data.
0 = RGMII receive clock is aligned to receive data.
The default value for both (DP83869HM and DP83867) is 0, for DP83869HM it's shifted mode, for DP83867 it's aligned mode. Are these descriptions correct?
