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XIO2001: Issues at n40C

Gregory Duperon
Expert 6040 points
Part Number: XIO2001

I'm having issues when I send multiple write commands in quick succession while at -40C.  The XIO2001 asserts a PCI reset and stops responding to PCIe commands.

I am able to enumerate the PCIe and then PCI interfaces and send data over the bus. I find that when I issue two write commands (with PCI wait states) of 0xFFFFFFFF in rapid succession at -35C or below then the XIO2001 will issue a PCI reset and will break PCIe enumeration.  I've found that both the 3.3V and 1.5V rails are stable and that GRST# and PRST# are both held high.

If I write 0xAAAAAAAA or 0x55555555 then the error does not happen. I also do not experience the failure at room temperature or when the PCI bus has no wait states.

Any suggestions?

  • 0
    TI__Expert 7935 points

    Gregory,

    Are you using an EVM or some other system /card with the XIO2001 on it?  How many devices have you tested?

    Regards,
    Davor

  • 0 in reply to Davor Glisic
    Prodigy 20 points

    Hey Davor,

    We are not using an EVM. We designed our own PCB. The product has been working fine for years, but we probably never tested writing 0xFFFFFFFF multiple times while at cold. So far we are seeing the issue on 3 units but we are building up more to test.

    Thanks,
    Dan

  • 0 in reply to Dan Benz
    TI__Expert 7935 points

    Hi Dan,

    We haven't seen a report of a similar issue.  Let us know the failure rate when you have more units tested. 

    Regards,

    Davor

  • 0 in reply to Davor Glisic
    Prodigy 20 points

    Hey Davor,

    We have tested 10 more units and seen the same failures. We have also hooked up both a PCIe and PCI analyzer to both sides of the XIO2001. I can provide either to you if you would like to see. The PCIe trace looks valid. The only thing of note is that the same TLP gets NACKed a few times which triggers a link retraining. More concerning is the PCI side where we have seen a few different errors. In one recording the XIO2001 asserts FRAME# for many (~10,000) clocks without moving on to the data phase of the write transaction. In another recording we see the DEVSEL# line not asserted by the slave device and the XIO2001 never moves on to retry the transaction (It should time out after 6-8 cycles).

    Thanks,
    Dan

  • 0 in reply to Dan Benz
    TI__Expert 7935 points

    Hi Dan,

    At this point, it is probably best to engage with the TI Quality team. I suggest providing a couple of units to your local TI contact who can pass it down further.

    Regards,

    Davor