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[FAQ] DS280DF810: How to use SigconArchitect to program 16-bits User Defined Generator Pattern
Part Number: DS125DF410
When for some reason, you are not feeling well, you go to a doctor and after some questions and answers you get a prescription trying to address the immediate problem you are having. When a CDR or retimer is not achieving lock, we are the doctors and the CDR is not talking back. But we can devise different experiments to find the root cause. One of the reason could be related to a non-ideal reference clock. In this FAQ, we can test if reference clock could be causing the device to not lock.
DS1xxDFxxx needs a stable 25MHz +/-100ppm reference clock to lock to the incoming signal. This reference clock is synthesized and enables the CDR to check incoming signal data rate. If for some reason incoming signal ppm is way off, compared to the synthesized 25MHz-clock - then it will not get qualified and CDR lock is not achieved. Given this, it is important to have a reliable reference clock. Steps below instructs the CDR to NOT use the reference clock and use a wide range of incoming signal rates to achieve lock. Given steps below, if CDR achieves lock then loss of lock is due to the reference clock.
RAW FF 0C FF //enable smbus write to all channel
RAW 36 01 FF //operate the CDR with no reference clock
RAW 0A 1C FF //reset CDR
RAW 0A 10 FF //release reset
RAW 02 00 00 //read CDR status. If bits 3&4 are set, CDR has achieved lock
If we execute above steps and device is not locking then issue is not related to the reference clock.
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