Hi team,
I want to know why the midpoint of RD/TD is pulled up to Vdd as I marked on the screenshot, is it a must? I see some 100M PHY transceivers is pulled down to GND via 0.1uF capacitor. Thanks advance and looking forward to your feedback.
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Hi team,
I want to know why the midpoint of RD/TD is pulled up to Vdd as I marked on the screenshot, is it a must? I see some 100M PHY transceivers is pulled down to GND via 0.1uF capacitor. Thanks advance and looking forward to your feedback.
Hi William,
The DP83848 requires pullup resistors on the data lines by design. They must also be 1% tolerance
Thanks,
Cecilia