TDP158: TDP158: can detect monitor name but no video show in monitor

Hi,

Are you using a DP++ or a HDMI source? Can you please share the schematic?

Thanks

David

The source is the output of an FPGA's SERDES, with the FPGA running HDMI IP. We have used this in the past, but not with the tdp158.

We don't use the DDC, as the monitor resolution is fixed.

Hi,

Looking at the schematic, the SCL_SRC and SDA_SRC need to be pulled to GND. The SDA_SNK and SLC_SNK need to be connected to the DDC bus between the FPGA and the HDMI connector.

You said the FPGA running HDMI IP, do you know if the FPGA supports DP++?

Thanks

David

The monitor connected to this device has a DVI input and not HDMI. There will be no traffic on the DDC lines. Will the device work?

The FPGA is an Arria 10 and is running HDMI IP. The use of this device in our application was discussed with TI prior to designing it in. Will this device work  with DVI/HDMI (1 clock, 3 colors) input?

Hi, 

The DP158 supports an AC coupled digital video interface (DVI) or high-definition multimedia interface (HDMI) signal input. 

For DVI application, the DP158 doesn't care the DDC bus, but I would still terminate unused SDA/SCL_SRC and SDA/SCL_SNK.

Does the FPGA output require to be AC-coupled or DC-coupled? If the FPGA output require to be DC-coupled, and with the current input being AC-coupled, then you need to place 50ohm termination network between the FGPA output and the AC-coupling capacitors. 

Do you have a scope that you can probe both the input and output of the DP158?

Thanks

David

The input requires AC coupling from the FPGA, which is present. I am out of the office until next week and can't get scope pictures, but when I checked them yesterday, the input signals were present (clock & data) at ~800mv differential . The output was DC at 3.3V (the tmds pull ups from the monitor). So, if the SDA/SCL_SRC are grounded (simplified schematic in datasheet) and pull ups are added to _SNK, the device will redrive the input? 

What logic is in the device that prevents the operation with these signals as open?

Hi,

DDC should not impact the DP158 operation. 

As long as the HPD_SNK is high and valid data is at the DP158, the DP158 will output data when HPD_SNK is high.

Thanks

David

Attached are the scope images for the 4 input channels. Given your comment above, the DDC pins can be left open & the device should still provide the output.TI_waveforms.pdf

In section 10.1, it states that when the TDP158 goes into low power mode (HDP low, cable un-plugged), and the TMDS_CLOCK_RATIO bit is cleared and HDMI 2.0 resolutions require the bit to be set by I2C. This would imply that the device can't be used in pin-strap mode and support HDMI 2.0. Correct?

Hi, 

As part of discovery the source reads the sink E-EDID information to understand the sink’s capabilities. Part of this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine the data rate supported. Depending upon the value the source will write to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. In both the I2C and the pin-strap mode, the TDP158 snoops the DDC link to determine the TMDS clock ratio status and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a ‘1’ is written by the source the TMDS clock is 1/40 of TMDS bit period. If a ‘0’ is written, then the TMDS clock is 1/10 of TMDS bit period.

If the TMDS181 comes out the low power mode, you can force the TMDS_CLOCK_RATIO_STATUS to be set by un-plug/plug the cable in the pin-strap mode.  

But for the DVI application, this doesn't matter as the TMDS_CLOCK_RATIO_STATUS will be set to 0. 

I am looking at the scope image and it looks like the channel 3 waveform looks very odd. Can you check on the output as well and see if the DP158 is driving the output?

Thanks

David

TMDS181?? How does that relate to the TDP158?

From my understanding, the TDP158 is a redriver and not a retimer. Correct? What function does the clock ratio have on the redriver? Is it only used to qualify the period of the input clock?

Does the clock ratio bit only control (automatically) the source termination?

Hi,

Sorry, this is a typo on my part. It should be the DP158, not the TMDS181.

The clock ratio bit does two things:

1. Set the TMDS bit period to 1/10 for HDMI1.4 and 1/40 for HDMI2.0. 

2. The DP158 TX termination automatically changes to HDMI2.0 75-150ohm when the clock ratio bit is 1, or can be set to No Termination or 150-300 when the clock ratio bit is 0.

Thanks

David  

If the device is a re-driver, then the tmds bit period is going to be controlled by the sourcing input clock. What is the 158 doing when set to 1/40'th? Does it change the output characteristics (besides impedance)?

Hi,

The DP158 TX has its own TX SWING (adjusted with VSADJ), pre-emphasis, and slew rate control, so the output characteristic will be different from the FPGA output characteristic.

Thanks

David

Both of these items are controlled by either the pin strapping or the I2C registers. Does the device also alter these based on the level of the clock ratio bit? If so, that doesn't appear to be indicated in the datasheet.

Hi,

No, the SWING, Pre-emphasis, and the slew rate are independent from the clock ratio bit.

Thanks

David

I don't see the changes in the pre-emphasis or slew rate, based on this bit, outlined in the datasheet. Can you point me to the section?

Hi,

The clock ratio bit will not impact the pre-emphasis or the slew rate.

Thanks

David

You state above "1. Set the TMDS bit period to 1/10 for HDMI1.4 and 1/40 for HDMI2.0. "

What does that do in the part?

Hi,

This is reference to the source. When the clock_ratio is 1, the TMDS clock is 1/40 of TMDS bit period. When the clock_ratio is 0, then the TMDS clock is 1/10 of TMDS bit period.

With the DP158 being a redriver, the clock_ratio will only impact the TX termination when the TX termination automatic selection is enabled. Otherwise it will have no impact on the DP158.

Thanks

David