Hello,
We have been using the DP83848-EP in our Ethernet system for some time now but what we are seeing that we are unable to establish link approximately 50% of the time. The only way to establish link is to power cycle the board until it works or manually pull the RESET line low. What we found is that when we power up in a faulted state the component is indicating that it is in a Bad SSD state. This can be proven by measuring the RX_ER and the RXD[3:0]=1110. When connecting the RX_ER line up to a o-scope what we see is that this line will be HIGH and "pulse" LOW every ~16uSec for ~100nSec. Another key point about our set up is that we are not sending any commands/messages to he PHY chip during this time, we only have it connected to a laptop running wireshark. Also what we have found is that we only see this off nominal condition with certain code loads on our FPGA, there is no issue with some code loads. We have looked at the power up plots (X1 CLK, Reset, 3.3V, etc.) and everything looks nominal.
What it looks like to me is that the PHY chip is thinking that it is receiving a message and expecting the /J/K/ pattern and not receiving it. Then getting stuck in some kind of loop until we reset or power cycle
Have you seen anything like this before? Is there something about how we initialize the PHY chip with the FPGA that could cause this condition?
Thank you,
Andrew Wiley