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TCA9517: Multiple TCA9517's for I2C bus extension

Part Number:

Hello,

I'm seeing some issues once I use more than three TCA9517's in series to extend my I2C bus (operating at 400khz, but 100khz also sees the same issue).

Firstly, this design I accidentally swapped SCL/SDA ports of the chip. Can you please confirm that the internals of the chip are identical (as the datasheet suggests) and the following issue is not due to that?

The main issue is looking at the logic analyzer and scope traces it seems the waveform duty cycles are being distorted quite a bit. It seems this might be due to the asymmetric propagation and transition times between L to H and H to L? For every TCA9517 added to the chain the duty cycle increases slightly (longer high period), which is very evident on the SCL line which is typically supposed to be a square wave and goes rectangular very quickly. 

For reference, my design has these setup so the Master is connected to the A-side of the TCA9517, and the B-side is connected to the A-side of the next TCA9517. These are strung along in this way.
The edges look quite clean but I can capture a scope trace if we need to take a look-- particularly the falling edge is very sharp and the rising edge seems pretty crisp for 400khz I2C. The pull-ups on these boards are 2.2k (and in some cases, it's effectively 1.1k), there is actually not a lot of capacitance on the bus either.

The net effect is that there are spurious stop events because SDA transitions start happening during a SCL-High time period. You can see this in the logic analyzer output with the Red circles. (the logic analyzer corroborates what the device on that bus is seeing and the sope seems to see this as well). 

Has this been seen before? How many series TCA9517's have used in designs?

Thanks for your help!

  • Andrew Beaulieu said:

    Part Number: TCA9517

    Hello,

    I'm seeing some issues once I use more than three TCA9517's in series to extend my I2C bus (operating at 400khz, but 100khz also sees the same issue).

    Firstly, this design I accidentally swapped SCL/SDA ports of the chip. Can you please confirm that the internals of the chip are identical (as the datasheet suggests) and the following issue is not due to that?

    [Bobby] Internally they are identical so this should not actually cause any issues.

    The main issue is looking at the logic analyzer and scope traces it seems the waveform duty cycles are being distorted quite a bit. It seems this might be due to the asymmetric propagation and transition times between L to H and H to L? For every TCA9517 added to the chain the duty cycle increases slightly (longer high period), which is very evident on the SCL line which is typically supposed to be a square wave and goes rectangular very quickly. 

    [Bobby] That's correct, since prop delays cause signal distortion, the duty cycle of the input compared to the output will be longer on the lows. One reason is due to an 'unwrapping' affect on B side which causes it to sit low at ~0.54V until A side rises up. This will stretch the low periods.

    For reference, my design has these setup so the Master is connected to the A-side of the TCA9517, and the B-side is connected to the A-side of the next TCA9517. These are strung along in this way.

    [Bobby] This sounds like its set up correctly (on paper atleast) since B sides are never allowed to be connetced, you would need to connect A to B if you were to stack these guys in series.
    The edges look quite clean but I can capture a scope trace if we need to take a look-- particularly the falling edge is very sharp and the rising edge seems pretty crisp for 400khz I2C. The pull-ups on these boards are 2.2k (and in some cases, it's effectively 1.1k), there is actually not a lot of capacitance on the bus either.

    The net effect is that there are spurious stop events because SDA transitions start happening during a SCL-High time period. You can see this in the logic analyzer output with the Red circles. (the logic analyzer corroborates what the device on that bus is seeing and the sope seems to see this as well). 

    [Bobby] It may help if you show a normal o-scope shot since the logic analyzer doesn't show much of the analog portion of the signal.

    One zoomed in shot of the falling waveform of each would also help (with high sampling and resolution). Sometimes the inductance from the cabling causes undershoots which damage the device over time. We should make sure this isn't happening.

    [Bobby] A few years ago, I heard someone tried to use ~22 buffers in series before but he was aiming for a much lower frequency of use. I don't know if he did it successfully though. One other case, I heard something like 8 being use for some temperature/humidity sensing application for an agriculture project. 


    Thanks for your help!

    [Bobby]

    Could you also provide a schematic of your TCA9517s?

    How long are the cables between the two TCA9517s?

    How many are you attempting to stack in series? (5x?)

    -Bobby

  • Hi Bobby,

    Thanks for the responses. I was able to actually get this mostly working with changing to a "B to A" design with this chip. After quite a few hops the signal does degrade (timing issues again) but I'm able to extend it further by reducing the bus speed. I haven't gone through this analytically yet to understand why this is works in this case, but maybe you could offer some insight?

    Unfortunately, I don't have have any good scope captures of the above A to B setup (I have been using an old scope at home for most of this) but the above logic analyzer does actually reflect things quite well and it was easier to pick up on timing issues with it. The rise and fall of the SDA and SCL do look rather clean (the pullups are pretty hard on the design)

    BOBBY said:

    [Bobby]

    Could you also provide a schematic of your TCA9517s?

    How long are the cables between the two TCA9517s?

    How many are you attempting to stack in series? (5x?)

    -Bobby

    Here is the part of the schematic with the TCA9517. There is a device on the SDA1/SCL1 side.
    With chaining this device along as labeled with In and Out, the above failures happen after a couple of hops. Reversing that completely (using Out as In and In as Out) allows this to work beyond 10 devices, but dependent on bus speed. I was hoping to use the multiple Outs to split the bus, but with the "B to A" change, this gets a little complicated.

    The cables between the TCA9517s are quite short right now, about 100mm. In the future I may consider making them longer but probably not too much. I2C without the repeater could probably actually work for many of these "hops" through the board, but I was hoping to keep the design monolithic (repeaters used on all of these, not just choosing "repeat boards."

    Ideally, I'd stack around 20 of them. I'd say about 10x would be a minimum, ideally at 400kHz bus speed.