Hello,
I'm seeing some issues once I use more than three TCA9517's in series to extend my I2C bus (operating at 400khz, but 100khz also sees the same issue).
Firstly, this design I accidentally swapped SCL/SDA ports of the chip. Can you please confirm that the internals of the chip are identical (as the datasheet suggests) and the following issue is not due to that?
The main issue is looking at the logic analyzer and scope traces it seems the waveform duty cycles are being distorted quite a bit. It seems this might be due to the asymmetric propagation and transition times between L to H and H to L? For every TCA9517 added to the chain the duty cycle increases slightly (longer high period), which is very evident on the SCL line which is typically supposed to be a square wave and goes rectangular very quickly.
For reference, my design has these setup so the Master is connected to the A-side of the TCA9517, and the B-side is connected to the A-side of the next TCA9517. These are strung along in this way.
The edges look quite clean but I can capture a scope trace if we need to take a look-- particularly the falling edge is very sharp and the rising edge seems pretty crisp for 400khz I2C. The pull-ups on these boards are 2.2k (and in some cases, it's effectively 1.1k), there is actually not a lot of capacitance on the bus either.
The net effect is that there are spurious stop events because SDA transitions start happening during a SCL-High time period. You can see this in the logic analyzer output with the Red circles. (the logic analyzer corroborates what the device on that bus is seeing and the sope seems to see this as well).
Has this been seen before? How many series TCA9517's have used in designs?
Thanks for your help!