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Original question:

DP83867IR: DP83867 1000-BASETX Configuration

DP83867IR: DP83867IR

bahram afghani
Prodigy 170 points
Part Number: DP83867IR
Other Parts Discussed in Thread: DP83867E

Hi TI team,

My board is using 2 x DP83867E phys. How do I verify the EYE diagram at the the end of the cable.

I am assuming that I have to use 2 Phys connecting via a CAT6. Configure the master phy to generate continuous PRBS packet and configure the slave phy to function as a LOOPBACK then probe MDI channel A of slave phy.( applying the test only to Channel A)

Is that the right way to verify the EYE at the end of the cable?

Also can you please provide the register programming stpes and values to achieve above?

Many Thanks,

Bahram

  • 0
    TI__Genius 16025 points

    Hello Bahram,

    Which mode is 867 used? 100Mbps or 1000Mbps? Electrical specs of ethernet output is tested by IEEE compliance tests and defined structures. You may refer to Tektronix TDSET3 test suite for different tests.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 170 points

    Hi Vikram,

    1000Mbps mode is the answer. I am connecting a master phy (PRBS generator) to a slave phy (loopback phy) via a short CAT6 cable.

    I am probing the A channel of each PHY to capture the TX and RX EYEs, following the instructions listed below, I am NOT seeing any EYE forming on the scope, wonder what am I missing!!!

    FYI; PRBS phy is at address '0'  and  loopback phy is at address '1'.

    Again, the attempt is to place PHY at address 0 in PRBS mode and the other phy in loop back mode.

    Here are the instructions:

    //Master phy PRBS mode

    phywr 0 0x001F 0x8000 ; write 0x8000 to phy at address 0 register  0X001F (HW RESET)

    phywr 0 0x0000 0x0140 ; force 1G

    phywr 0 0x00FE 0xE720 ; set for loopback

    phywr 0 0x0010 0x5028 ; disable auto MDIX

    phywr 0 0x0016 0xF000 ; BIST PRBS only (no internal loopback)

    phyrd 0 0x0017; read register 0x0017 of phy at address 0 (PRBS status: reads back 0x0240)

    phywr 0 0x0072 0x0003 ; PRBS lock and clear

    // Slave phy loopback mode

    phywr 1 0x001F 0x8000 ;  HW RESET

    phywr 1 0x0000 0x0140 ; force 1G

    phywr 1 0x00FE 0xE720  ;set for loopback configuration

    phywr 1 0x0010 0x5028 ;disable auto MDIX

    phywr 1 0x0016 0x0020 ; reverse loopback

    Thanks Vikram.

    Bahram

  • 0 in reply to bahram afghani
    TI__Genius 16025 points

    Hi Bahram,

    Is link established between link-partners? Kindly read register 0x0001 to know the link-status. 

    Also do share the reason for capturing data like this as this is not the way we check electricals of ful duplex channel. May be I will be able to help you find another way to solve your target problem.

    --

    Regards,

    Vikram 

  • 0 in reply to Vikram Sharma
    Prodigy 170 points

    Dear Vikram,

    I am trying to validate the EYE/ Jitter of any of the 4 channels. What is the easiest way to accomplish this? I will follow your instructions.

    Bahram

  • 0 in reply to bahram afghani
    Prodigy 170 points

    Hi Vikram,

    To start the link is established  when i externally connect the 2 phys with a CAT6 cable ( I read 0x796D on offset 1 of both phys). However as I start configuring the registers with the above mentioned values, link dies. (I read 0x7949 on offset 1). Obviously writing 0x8000 to offset 0x1F to either phys, brings the link back up.

    Look forward to your feedback.

    Thanks,

    Bahram

  • 0 in reply to bahram afghani
    TI__Genius 16025 points

    Hello Bahram,

    Refer to TDSET3 test suite of Tektronix or IEEE standard document. The electrical specs of each channel are measured by analysing each channel with output standalone and with a defined load.

    --

    Regards,

    Vikram