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DS250DF810: ds250df810

Part Number: DS250DF810

Hi,

  I use DS250Df810 as retimer. when it work at 10G, it VEO = 0.5 HEO=0.5. Data path also OK. when it run at 25G, VEO=168 ~ 250 HEO = 350 ~ 430, it will has packet error and FEC error. I change 3 type of RX EQ/DFE, it still can not get better. Do you has other suggestion can improve RX? 

thanks

cannie

  • Hi,

    • What is the retimer input channel approximate insertion loss for 25Gbps?
    • Is there any Tx post-cursor de-emphasis being applied on the input signal to the retimer?

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 1. direct connect SFP signal into retimer chip rx.

    2. NO, it come from SFP directly.

  • Hi,

    You may try forcing Rx CTLE = 0x00 on the retimer channel in question to see if the eye opening values improve. See channel register write routine below.

    Table. Force CTLE Boost Value of 0

     

    STEP

    SHARED/ CHANNEL REGISTER SET

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

    COMMENT

    1

    Channel

    Write

    2D

    08

    08

    Enable CTLE boost override

    2

    Channel

    Write

    03

    00

    FF

    Set CTLE boost to 0x00.

  • ds250.doc

    hi,

      it still can not work.

    br,

    cannie

  • Hi,

    In addition to forcing CTLE = 0x00 try the retimer channel register settings below. We recommend these settings for Rx input over-equalization cases. You may apply these settings via the SigCon Architect GUI Low-Level Page.

    REG       Value    Mask     Comment

    13           04           04           //Enable CTLE limiting output mode

    1A          00           08           //Reduce CTLE bias current, to reduce the applied boost

  • Hi, 

      It getting better, I will do more test.

    thanks

    cannie

  • Hi,

       I still will has error.

    Br,

    cannie

  • Another retimer configuration suggestion would be to disable the limiting mode, but keep the reduced CTLE bias current setting. Then, the customer may implement the EQ optimization procedure below to both fix CTLE = 00 and also apply post-cursor attenuation via the DFE tap 1. We typically recommend this procedure for cases of severe retimer input over-equalization due to very low input channel loss. Do note that TI recommends a minimum retimer input insertion loss of 3-4dB.

     

        • REG       Value    Mask     Comment

          13           00           04           //Disable CTLE limiting output mode

          1A          00           08           //Reduce CTLE bias current, to reduce the applied boost

           

          REG                        Value                    Comment

          1E                           E3                           Enable DFE

          0x12[7]                  0                             Set DFE tap 1 polarity to 0

          Loop for optimizing the DFE attenuation setting

          REG                                Value                             Comment

          0x12[4:0]                      0x02‐0x1A                    Set DFE tap 1 to desired weight

          0x0A                              0x0C                               Puts the CDR into RESET

          0x0A                              0x00                               Releases the CDR from reset

          0x02[4]                                                                  Read CDR lock status

          0x27                                                                       Read HEO

          0x28                                                                       Read VEO

          Note: It is recommended to allow for ~20ms wait time after implementing a CDR reset and

          release operation

  • Hi,

       could you provide register 0x1A definition? my datasheet show reserved,

    Thanks

    cannie

  • Hi,

    Yes the other bits in register 0x1A are RESERVED. I cannot share those, as they are not intended for customer use.

    Regards,

    Rodrigo

  • Hi,

       for CDR bypass, I did below:

    0x1E[7:5] =0

    0x09[5]=1

    0xA5[7:5]=0

     Do I still miss some configuration?

    Br,

    cannie

  • Hi Cannie,

    For the function to work, 0x09[5] needs to be kept at its default value of 0. refer to the programming guide register descriptions below.

    1E

    7

    1

    RW

    Y

    PFD_SEL_DATA_PRELCK[2]

    Output mode for when the CDR is not locked. For these values to take effect, Reg_0x09[5] must be set to 0, which is the default.

    000: Raw Data

    111: Mute (Default)

    All other values are reserved. (see

    Section 6.34)

    6

    1

    RW

    Y

    PFD_SEL_DATA_PRELCK[1]

    5

    1

    RW

    Y

    PFD_SEL_DATA_PRELCK[0]

    4

    0

    RW

    N

    SER_EN

    1: Enable serializer (used for PRBS Generator)

    0: Normal operation. Disable serializer.

    3

    1

    RW

    Y

    DFE_PD

    This bit must be cleared for the DFE to be functional in any adapt mode.

    1: (Default) DFE disabled.

    0: DFE enabled

    2

    0

    RW

    Y

    PFD_PD_PD

    1: Power down PFD phase detector.

    0: Normal operation. Enable PFD

    phase detector.

    1

    0

    RW

    Y

    EN_PARTIAL_DFE

    1: Enable DFE taps 3-5. DFE_PD

    must also be set to 0.

    0: (Default) Disable DFE taps 3-5.

    0

    1

    RW

    Y

    PFD_EN_FD

    1: Normal operation. Enable PFD

    frequency detector.

    0: Disable PFD frequency detector.

     

    ADDRESS (Hex)

    BITS

    DEFAULT VALUE (Hex)

    MODE

    EEPROM

    FIELD NAME

    DESCRIPTION

    A5

    7

    0

    RW

    Y

    PFD_SEL_DATA_PSTLCK[2]

    Output mode for when the CDR is in lock. For these values to take effect, Reg_0x09[5] must be set to 0, which is the default.

    000: Raw Data

    001: Retimed data (default)

    100: PRBS Generator or Fixed

    Pattern Generator Data

    101: 10M clock

    111: Mute

    All other values are reserved. (see

    Section 6.35)

    6

    0

    RW

    Y

    PFD_SEL_DATA_PSTLCK[1]

    5

    1

    RW

    Y

    PFD_SEL_DATA_PSTLCK[0]

    4

    0

    RW

    N

    RESERVED

    RESERVED

    3

    0

    RW

    N

    RESERVED

    RESERVED

    2

    0

    RW

    N

    RESERVED

    RESERVED

    1

    0

    RW

    N

    RESERVED

    RESERVED

    0

    0

    RW

    N

    RESERVED

    RESERVED

    Cordially,

    Rodrigo