SN65DSI86: single channel application support 1920x1080 resolution

Ann Lien

Assume pixel clock = 148.5MHz, with 24BPP, we would have 

Stream bit rate = 148.5 * 24 = 3.564Gbps

Min DSI Clock = Stream bit rate / (2 * DSI lane) 

Max DSI clock frequency is 750MHz. So you would need 4 DSI lanes to not violate the 750MHz requirement.

Thanks

David