Host needs to identify serializer as monitor of different type than provided by "Internal pre-programmed EDID" and we're looking at "Internal EDID loaded into device memory" as a way to accomplish this.
7.3.4.2 Internal EDID (SRAM)
The DS90UB949A-Q1 also allows the internal loading of an EDID profile up to 256 bytes. This SRAM storage is
volatile and requires loading from an external I2C master (local or remote). The internal EDID is reloadable and
readable (local/remote) from control registers during normal operation.
It's not clear from the data-sheet (SNLS650 –MAY 2019) how this is done however.
Control registers assumed to be involved:
-
0x47 BRIDGE_CTL
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0x48 APB_CTL
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0x50 BRIDGE_STS
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0x51 EDID_ID
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0x52 EDID_CFG0
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0x53 EDID_CFG1
-
0x54 BRIDGE_CFG
But exactly how is unclear. In this mode it's assumed that an external eeprom is not needed (see also related question below).
On a related note: Should the only viable option be "External local EDID (EEPROM)" How is that supposed to work? Do you suggest allowing the i2c-bus to have two masters as an MCU is already controlling the DS90UB949A-Q1 or does there an exist an implicit ordered sequence in which MCU/DS90UB949A-Q1 are supposed to cooperate (multi-mastered bus) or do we need an i2c-switch?
Please advise