Part Number: DS125MB203
We are using the DS125MB203SQ part for PCIe.
We are using one Edge connector and one mini PCIe connector and selection is controller through SEL 0 pin,
The device is connected to FPGA on one side(Supports Gen 3) and PCIe Edge conn and MPCIe connector on the other side.
We right now are using PCIe edge connector only with FPGA acting as an endpoint.
We are facing the issue, we are able to link up only at GEN 1, but our device support GEN 3.We need to get a link up at GEN 3.
Please see some more information below:
The track length from FPGA to DS125MB203SQ is around 3.5 inch and from DS125MB203SQ to PCIe edge connector is 1 inch.
PFA Schematic for the same, Kindly reviews and let us know the possible solutions.
Hi, some follow up questions to facilitate my debug:
HSSC Applications Engineer
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.