DP83867IR: TX Interface skew between different input types as it relates to timing

John Lally

Part Number: DP83867IR

This is a related post to the post by Stephen Zinck, posted on May 18, 2020 at 3:13pm.

We are seeing the same phenomena in our SI sims, i.e. the differences in loading on TX_D0 & TX_D1 (GPIO_SGMII_IN model) versus the TX_CLK, TX_CTRL & TX_D(3:2) (GPI model) is causing skew across the Tx RGMII bus.

Does the timing parameter IOskew=0.35ns in Table 3 of snla243 include the skew caused by the differences in input loading or should we add the skew we're seeing in our SI sims to the IOskew=0.35ns specified in snla243?

Or perhaps is the input loading skew included in one of the other delay parameters specified in snla243 ?

Please advise, thanks,

-John

over 3 years ago

0 Cecilia Reyes over 3 years ago

TI__Genius 9920 points

Hi John

GPIO_SGMII only has an extra capacitance at its input, when used in input mode which is why you may be seeing the extra loading compared to the other GPI pins.

Since the GPI models do not have the series resistors included in the models that is where it differs.

Have you confirmed whether you are modeling and testing the GPIO pins as input or output?

Thanks,

Cecilia

0 John Lally over 3 years ago in reply to Cecilia Reyes

Intellectual 505 points

Thanks for the follow up Cecilia,

There is no switch that we can see, these are discrete input only buffer models.

dp83867.ibs

-John

0 Cecilia Reyes over 3 years ago in reply to John Lally

TI__Genius 9920 points

Hi John,

Can you share a capture of your simulation schematic as well as the scope capture of the waveforms? I think you only attached the PHY ibis model in the thread.

Thank you!

Cecilia

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DP83867IR: TX Interface skew between different input types as it relates to timing