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[FAQ] SN65DSI86: SN65DSI86 Black Screen Debugging Guide

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Part Number: SN65DSI86

How do I debug the SN65DSI86 black screen issue?

  • For SN65DSI86, there are multiple possible causes for the black screen. When debugging the issue of a black screen, we need to take a look at each of them.

    1. Debugging using the SN65DSI86 Status Register (0xF0 - 0xF8)

    The status registers located at offsets 0xF0 thru 0xF8 can provide valuable information on failures which can result in black or flickering panel.

    Addresses 0xF0 thru 0xF3 report errors associated with the DSI interface. Sometimes errors flags can be set at power-on or during start of the DSI stream. For this reason, it is recommended to clear flags by writing 0xFF and then reading back status flags. The bits which remain set are the errors which should be focused on. Typically errors set in these fields indicate signal integrity issues. Recommend verifying setup/hold meet DSI86 requirements. Also, adjustment of the RX EQ located at register offset 0x11 may help.


    Address 0xF4 report errors associated with AUX communication. AUX communicate typically fails when attempting to communicate with the eDP panel when the panel is not ready. Typically, the panel indicates it is ready when HPD is high. Also, REFCLK frequency not being correct can cause AUX failures.
    Address 0xF5 reports status of HPD. This register is provides status of HPD. This register is only useful if HPD is enabled (register 0x5C bit 0 (HPD_DISABLE) is cleared).


    Address 0xF6 thru 0xF7 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers.


    Address 0xF8 report errors associated with DisplayPort link training. Signal integrity issue may be a cause of the failures. It may be necessary to reduce eDP data rate and/or reduce the number of DP lanes to correct link training issues. It also may be necessary to change DSI86’s Link Training Look-Up-Table default values. The LT LUT is located from register 0xB0 thru 0xC3. The LT LUT contains transmit voltage swing level and pre-emphasis levels used during the link training process.

    2. eDP Panel is not enabled for ASSR

    It is possible to have no error flags set in registers 0xF0 thru 0xF8 but the eDP panel is still black. ASSR not being enabled in panel is possible cause. The DSI86 defaults to ASSR enabled. In the default configuration, software must enable ASSR in the panel before the start of link training. Below are steps to enable ASSR in panel.


    1. Write 0x01 to register 0x64.
    2. Write 0x00 to register 0x74.
    3. Write 0x01 to register 0x75.
    4. Write 0x0A to register 0x76.
    5. Write 0x01 to register 0x77.
    6. Write 0x81 to register 0x78.

    3. eDP Panel doesn’t support ASSR

    All eDP panels support standard DP scrambler seeds. It is possible that the eDP panel doesn’t support ASSR. If this is the case, DSI86’s ASSR will need to be disabled by making ASSR_CONTROL read/write instead of read-only. The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:
    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    Best Regards
    David

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