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SN65DSI84: LVDS singal behavior checking

Mars Huang3
Prodigy 30 points
Part Number: SN65DSI84

Hi Sir,

Now we have one different behavior on LVDS signal between the board of EVT and DVT. In the EVT board, the LVDS signal will be off immediately when power down. However, in the DVT board, the LVDS will be off after about 2s when power down.

Basically, the schematic is the same. Attachment is the schematic of DVT and the waveform of EVT board and DVT board.  Could you please help to check why the behavior is difference? Thank you.

ND108T_R0B_SCH_1102_MIPI to LVDS_CA.pdf

BR,

Mars

cid:image002.png@01D6B174.FD5E59B0   cid:image003.png@01D6B174.FD5E59B0
 
  • 0
    TI__Mastermind 35130 points

    Hi Mars,

    Your screenshots only show DSI_LVDS_BL_EN. When you say power down, are you also powering down LVDS_VCC_1P8?

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 30 points

    Hi I.K,

    No, the  DSI_LVDS_BL_EN is from our SOC GPIO pin which is 3.3V Level. The  DSI_LVDS_BL_EN is connected to our discrete circuit.

    My point is

    1. Do you have any idea about why the LVDS singal has the different behavior between the EVT board and DVT about?  

    2. Is it possible to adjust the LVDS signal timing?

    3. Is there any problem on the schematic? 

    Thank you.

    BR,

    Mars

  • 0 in reply to Mars Huang3
    TI__Mastermind 35130 points

    Hi Mars,

    1. It may be due to differences in Vcc powerdown time or device variation

    2. No, there's no way to adjust the timing with the device

    3. I don't see any issues

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 30 points

    Hi I.K.

    Please see my feedback below. Thank you.

    1. The device is the same and the power rail is no any different. So does the SN65DSI84 have any sequence which relates to the LVDS signal

    2. OK

    3. The issue is the LVDS signal off time is too late, which will cause the DSI_LVDS_BL_EN off time is earlier than LVDS signal. The result will get a fail on panel sequence. We do the fine tune on DSI_LVDS_BL_EN, but the off time can not be later than LVDS signal. So do you have any idea for the issue? 

    Thank you.

    BR,

    Mars

  • 0 in reply to Mars Huang3
    TI__Mastermind 35130 points

    Hi Mars,

    Can you post a screenshot of Vcc powering down with the LVDS signals for both boards?

    The device does not have any sequence related to the LVDS signal. There is also no spec that defines how long it takes the LVDS signals to be off in relation to powering down Vcc. 

    Regards,

    I.K.