Hi All,
If you are encountering an issue with packet loss or CRC errors while using the DP83867, please consider some of these items for debug when using short cables.
Short cables at 1m or less in length for your device may experience signal quality issues. One reason could be that the digital signal processing internally may take too long to converge or may even converge incorrectly at shorter lengths which could result to a bad SNR - Signal to Noise Ratio. This then creates link dropping or potential packet losses which may require you to reset your device before beginning packet transfer again.
We have a script below that will be updated in the next revision of the DP83867 datasheet that should help eliminate any packet loss errors due to short cabling. This scripts allows for a change in the timing bandwidths to ensure the DSP converges correctly.
ADDR |
DATA |
Description |
0x001F |
0x8000 |
Hard Reset |
0x0053 |
0x2054 |
Threshold for consecutive amount of Idle symbols for Viterbi Idle detector to assert Idle Mode set to 5 |
0x00EF |
0x3840 |
CAGC DC Compensation Disable |
0x0102 |
0x7477 |
Master Training Timers - increasing time in different training states |
0x0103 |
0x7777 |
Master Training Timers - increasing time in different training states |
0x0104 |
0x4577 |
Master Training Timers - increasing time in different training states |
0x010C |
0x7777 |
Timing Loop Bandwidth |
0x01C2 |
0x7FDE |
Timing Loop Bandwidth |
0x0115 |
0x5555 |
Slave Timers - increasing time in different training states |
0x0118 |
0x0771 |
Slave Timers - increasing time in different training states |
0x011D |
0x6DB2 |
Timing Loop Bandwidth |
0x011E |
0x3FFB |
Timing Loop Bandwidth |
0x01C3 |
0xFFC6 |
Timing Loop Bandwidth |
0x01C4 |
0x0FC2 |
Timing Loop Bandwidth |
0x01C5 |
0x0FF0 |
Timing Loop Bandwidth |
0x012C |
0x0E81 |
FFE Fix |
0x001F |
0x4000 |
Soft Reset |
If you have further questions please start a new E2E thread and our Ethernet team can clarify these items further for you.
Thanks,
Cecilia