Original question:
SN65DSI84: Is it possible to check the LVDS test pattern even if the 0xe5 value is 1?
Hi,
Our test pattern appears, but the screen looks like a vertical line as shown below, and there is a feeling of flickering a little.
Our LVDS Display setting is below.
MIPI-DSI setting is below.
We're developing Android linux kenrel based on Qualcomm Snapdragon chip.
I appreciate any help.
Thanks.
Hi, I.K.
I have attached our dsi file.
and below is our MIPI DSI Source setting.
14 mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94a00 {
15 compatible = "qcom,mdss_dsi_pll_10nm";
16 label = "MDSS DSI 0 PLL";
17 cell-index = <0>;
18 #clock-cells = <1>;
19 reg = <0xae94a00 0x1e0>,
20 <0xae94400 0x800>,
21 <0xaf03000 0x8>;
22 reg-names = "pll_base", "phy_base", "gdsc_base";
23 clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
24 clock-names = "iface_clk";
25 clock-rate = <0>;
26 qcom,dsi-pll-ssc-en;
27 qcom,dsi-pll-ssc-mode = "down-spread";
28 gdsc-supply = <&mdss_core_gdsc>;
29 qcom,platform-supply-entries {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 qcom,platform-supply-entry@0 {
33 reg = <0>;
34 qcom,supply-name = "gdsc";
35 qcom,supply-min-voltage = <0>;
36 qcom,supply-max-voltage = <0>;
37 qcom,supply-enable-load = <0>;
38 qcom,supply-disable-load = <0>;
39 };
40 };
41 };
420 mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { 421 compatible = "qcom,dsi-ctrl-hw-v2.2"; 422 label = "dsi-ctrl-0"; 423 cell-index = <0>; 424 reg = <0xae94000 0x400>, 425 <0xaf08000 0x4>; 426 reg-names = "dsi_ctrl", "disp_cc_base"; 427 interrupt-parent = <&mdss_mdp>; 428 interrupts = <4 0>; 429 vdda-1p2-supply = <&pm8998_l26>; 430 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, 431 <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 432 <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 433 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, 434 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, 435 <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; 436 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", 437 "pixel_clk", "pixel_clk_rcg", 438 "esc_clk"; 439 qcom,null-insertion-enabled; 440 qcom,ctrl-supply-entries { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 444 qcom,ctrl-supply-entry@0 { 445 reg = <0>; 446 qcom,supply-name = "vdda-1p2"; 447 qcom,supply-min-voltage = <1200000>; 448 qcom,supply-max-voltage = <1200000>; 449 qcom,supply-enable-load = <21800>; 450 qcom,supply-disable-load = <4>; 451 }; 452 }; 453 }; |
this is our device tree source for panel.
|
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-force-clock-lane-hs;
qcom,mdss-dsi-lp11-init;
//qcom,mdss-dsi-bllp-power-mode;
//qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-panel-clockrate = <445500000>;
qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-lane-map = "lane_map_0123";
qcom,mdss-dsi-panel-timings = [00 1E 08 07 24 22 08 08 08 02 04 00];
qcom,mdss-dsi-t-clk-post = <0x0E>;
qcom,mdss-dsi-t-clk-pre = <0x34>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-width = <1920>;
qcom,mdss-dsi-panel-height = <1080>;
qcom,mdss-dsi-h-front-porch = <88>;
qcom,mdss-dsi-h-back-porch = <148>;
qcom,mdss-dsi-h-pulse-width = <44>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <36>;
qcom,mdss-dsi-v-front-porch = <4>;
qcom,mdss-dsi-v-pulse-width = <5>;
qcom,mdss-dsi-panel-framerate = <60>;
qcom,mdss-dsi-on-command = [
05 01 00 00 64 00 02 11 00
05 01 00 00 14 00 02 29 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
};
|
Could you give us guide?
Thanks.
Hi, I.K.
Thanks for your response.
I updated your link version so that window cut off is disappeared.
and I followed your step-by-step guide then found our LVDS horizontal setting issue & CLK issue.
Finally, I could see the result of output.
Could you recheck our setting is correct?
Hi I.K.
We have sent the panel datasheet PDF file.
Please check our mail. and our DSI CLK is exactly 445.5 Mhz.
And We're wondering about Data Enable Polarity, Horizontal Sync Polarity, Vertical Sync Polarity setting.
Our panel vendor said that our polarity settings are like below.
but when we changed those seeting, any register values are not change.
those value is not related to CSI registers?
Thanks
Choi
Regards,
Choi
