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Part Number: TCAN1042-Q1
Accordind to TCAN1042-Q1's datasheet, The TXD Dominant Timeout(DTO) interval is in 1.2 ms to 3.8 ms ,
When I try to measure the TCAN1042-Q1's DTO time, My measure value is about 51.7us , not in valid time interval,
what situation can cause this problem?
Interesting find. This does not look like the expected behavior of the dominant timeout feature. Could I ask a bit more about your test setup to see what else might be causing this apparently quick timeout?
1. What load/termination is present on the bus? Other transceivers, cabling, resistors? It looks like there's a small reflection on the M signal. I'm also interested to know if any overcurrent condition is being met, possibly from a short or low resistance between CANH and CANL.
2. Could you show CANH and CANL independently? I'm interested to see the symmetry of the two signals and what levels each is able to reach during dominant and recessive states.
3. What are the states of the other device pins during this test? Are any of the pin states being changed at/near the same time as the TX transition?
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In reply to Eric Schott1:
There are several CAN Transceiver on my schematic, I use breadboard to connector each CAN bus together. When I choose one of the CAN transceiver to transfer signal, the other will receiver this signal, and show it on console. all of the CAN Transceiver's DTO test are ok, but only this one has problem.
You mention if any of the pin states change at the same time when TX transition, so I monitor the STB(connect to MCU) pin's status, and I find it will change to high in about 50 us, then cut off the CAN bus.
The reason STB change to High is because the MCU are restart when I pull TX to ground, and the pin are in initialize state...
Anyway ,Thanks for your help!
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