• Resolved

TMDS181: No signal output when worked in 4K@60

Prodigy 70 points

Replies: 5

Views: 49

Part Number: TMDS181

Hi David,

I meet the same issue  when I used 4K@60.

https://e2e.ti.com/support/interface/f/138/t/947429?tisearch=e2e-quicksearch&keymatch=TMDS181

How to fix this issue in finally?

  • Hi,

    Are you able to see the video with 4k@30?

    Can you please share your schematic and TMDS181 page 0 and page 1 register dump? To access page 1 register, please write 0x01 to register 0xFF first, and then dump register from 0x00 to 0xB1.

    Can you also probe the TMDS181 clock output and verify the clock out frequency is 150MHz for 4k@60?

    Thanks

    David

  • In reply to David (ASIC) Liu:

    Hi David ,

    Thanks your quickly response.

    Yes ,4K@30 is ok.

    Please refer to the attachment for schematic and register dump.

    I upload " Register_TMDS181_4K@30" and "Register_TMDS181_4K@60" in the attachment.

    BTW,I have tried to configure the function mode to all of below modes and the termination ( 75 Ω to 150 Ω) for HDMI TX ,but the 4k@60 still can't work.

    DEV_FUNC_MODE. This field selects the device working function mode.
    00 – Redriver mode: 250 Mbps – 3.4 Gbps
    01 – Automatic redriver to retimer crossover at 1.0 Gbps (default)
    10 – Automatic retimer when HDMI2.0a based upon
    TMDS_CLOCK_RATIO_STATUS
    11 – Retimer mode across full range 250 Mbps to 6 Gbps

    distribute_output_card.pdfRegister_TMDS181_4K@30.txtRegister_TMDS181_4K@60.txt




  • In reply to David (ASIC) Liu:

    Yes ,I can probe the TMDS181 clock output is 150Mhz for 4k@60 in FPGA receive side.

    Info
    -----

    ------------
    HDMI RX SubSystem
    ------------

    ->HDMI RX Subsystem Cores
    : HDMI RX
    HDMI RX version : 03.00 (0403)

    HDMI RX Mode - DVI
    ------------
    HDMI RX timing
    ------------
    No HDMI RX stream
    Link quality
    ---------
    Link quality channel 0 : bad (65535)
    Link quality channel 1 : bad (65535)
    Link quality channel 2 : bad (65535)
    Audio
    ---------
    Format : Unknown
    Channels : 2
    ACR CTS : 0
    ACR N : 0
    Infoframe
    ---------
    RX header: 0

    ------------
    HDMI PHY
    ------------
    VPhy version : 02.02 (0000)

    GT status
    ---------
    RX reference clock frequency: 148498432 Hz
    DRU reference clock frequency: 125000000 Hz
    RX: CPLL
    RX state: ready

    CPLL settings
    -------------
    M : 1 - N1 : 5 - N2 : 4 - D : 1

    RX MMCM settings
    -------------
    Mult : 8 - Div : 1 - Clk0Div : 4 - Clk1Div : 8 - Clk2Div : 4

    DRU Settings
    -------------
    Version : 7
    DRU is disabled

    buffer:5,0040438780
    buffer:5,0040438780

  • In reply to Thomas Gan1:

    Hi,

    There are two issues with this design that I saw from the schematic.

    1. TMDS181 supports DC-coupled HDMI, for AC-coupled HDMI, you need to use the DP159. 

    2. The TMDS181 DDC snoop mode is not implemented. The DDC snoop mode needs to be implemented so the TMDS_CLOCK_RATIO_STATUS bit switch between HDMI1.4 (Register 0x0B bit 1 = 0) and HDMI 2.0 (Register 0x0B bit 1 = 1). If the snoop mode is not implemented, then you need to manually switch the TMDS_CLOCK_RATIO_STATUS bit between HDMI1.4 and 2.0.

    Thanks

    David

  • In reply to David (ASIC) Liu:

    Hi David,

    According to your suggestion ,4K@60 can work now.

    Thanks your great support.