TMDS181: TMDS181 no signal issue
Part Number: TMDS181
I meet the same issue when I used 4K@60.
How to fix this issue in finally?
Are you able to see the video with 4k@30?
Can you please share your schematic and TMDS181 page 0 and page 1 register dump? To access page 1 register, please write 0x01 to register 0xFF first, and then dump register from 0x00 to 0xB1.
Can you also probe the TMDS181 clock output and verify the clock out frequency is 150MHz for 4k@60?
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to David (ASIC) Liu:
Hi David ,
Thanks your quickly response.
Yes ,4K@30 is ok.
Please refer to the attachment for schematic and register dump.
I upload " Register_TMDS181_4K@30" and "Register_TMDS181_4K@60" in the attachment.
BTW,I have tried to configure the function mode to all of below modes and the termination ( 75 Ω to 150 Ω) for HDMI TX ,but the 4k@60 still can't work.
Yes ,I can probe the TMDS181 clock output is 150Mhz for 4k@60 in FPGA receive side.
------------HDMI RX SubSystem------------
->HDMI RX Subsystem Cores : HDMI RX HDMI RX version : 03.00 (0403)
HDMI RX Mode - DVI------------HDMI RX timing------------No HDMI RX streamLink quality---------Link quality channel 0 : bad (65535)Link quality channel 1 : bad (65535)Link quality channel 2 : bad (65535)Audio---------Format : UnknownChannels : 2ACR CTS : 0ACR N : 0Infoframe---------RX header: 0
------------HDMI PHY------------ VPhy version : 02.02 (0000)
GT status---------RX reference clock frequency: 148498432 HzDRU reference clock frequency: 125000000 HzRX: CPLLRX state: ready
CPLL settings-------------M : 1 - N1 : 5 - N2 : 4 - D : 1
RX MMCM settings-------------Mult : 8 - Div : 1 - Clk0Div : 4 - Clk1Div : 8 - Clk2Div : 4
DRU Settings-------------Version : 7DRU is disabled buffer:5,0040438780buffer:5,0040438780
In reply to Thomas Gan1:
There are two issues with this design that I saw from the schematic.
1. TMDS181 supports DC-coupled HDMI, for AC-coupled HDMI, you need to use the DP159.
2. The TMDS181 DDC snoop mode is not implemented. The DDC snoop mode needs to be implemented so the TMDS_CLOCK_RATIO_STATUS bit switch between HDMI1.4 (Register 0x0B bit 1 = 0) and HDMI 2.0 (Register 0x0B bit 1 = 1). If the snoop mode is not implemented, then you need to manually switch the TMDS_CLOCK_RATIO_STATUS bit between HDMI1.4 and 2.0.
According to your suggestion ,4K@60 can work now.
Thanks your great support.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.