DP83867IR: Link Down Conditions of 100M

Hi Ryo,

When the PHY links down, does link stay down or does it come back up again and resume data transfer? If you have register access during the link down, can you provide a read of the following registers:

• 0x0
• 0x1
• 0x4
• 0x5
• 0x9
• 0x10
• 0x11
• 0x32
• 0x6E
• 0x6F

Additionally, can you provide a schematic?

Thank you,

Nikhil

Hi Nikhil,

Thank you for your reply.

This scenario, because of link come back up again and resume data transfer, I can not read a registers during link down.

attached : schematic

/cfs-file/__key/communityserver-discussions-components-files/138/4212.Schamatic_5F00_Layout.pdf

Best Regards,

Ryo

Hi Ryo,

Even when link is down or a link partner is not connected, register access should be available if the PHY is properly powered on. I will review the layout and provide feedback by Monday.

Thank you,

Nikhil

Hi Nikhil,

I dumped the register with the link up at 100M.

DUT:
Autonegotiation :on
10/100/1000M : support
half/full : support
Auto-MDI/MDI-X : suport

Link Partner:
Autonegotiation :on
10/100M : support
half/full : support
Auto-MDI/MDI-X : suport

//

0h 1100
1h 796D
2h 2000
3h A231
4h 01E1
5h 41E1
6h 0067
7h 2001
8h 0000
9h 0200
Ah 0000
Bh 0000
Ch 0000
Dh 401F
Eh 0C5F
Fh 3000
10h D068
11h 6F02
12h 0000
13h 1C40
14h 29C7
15h 0000
16h 0000
17h 0040
18h 6B50
19h 4444
1Ah 0002
1Bh 0000
1Ch 0000
1Dh 0000
1Eh 0002
1Fh 0000
32h 00D3
6Eh 0000
6Fh 0100

Best Regards,

Ryo

Hi Ryo,

Thanks for providing a detailed register dump. I am looking into the schematic and register dump and will provide feedback by Monday.

Thank you,

Nikhil

Hi Ryo,

Some follow-up questions:

1. Are you writing to an registers? Default for register 0x0 should be 0x1140. What is the value of register 0x0 before link is up, without connecting the link partner? 

2. Can you provide a register dump upon power up before link is up, before connecting to the link partner?

3. From the schematic and register dump, it looks like all straps are default, only strap placed is to set RX_CTRL in mode 3. Can you confirm no other straps are placed?

Thank you,

Nikhil

Hi Nikhill,

Ans1.

 Yes, writing to an regisgers,after powr up

follow dump, no writing.

0h 3100
1h 7949
2h 2000
3h A231
4h 01E1
5h 0000
6h 0064
7h 2001
8h 0000
9h 0200
Ah 0000
Bh 0000
Ch 0000
Dh 401F
Eh 00D3
Fh 3000
10h D048
11h 0002
12h 0000
13h 0040
14h 29C7
15h 0000
16h 0000
17h 0040
18h 6B50
19h 4444
1Ah 0002
1Bh 0000
1Ch 0000
1Dh 0000
1Eh 0002
1Fh 0000
32h 00D3
6Eh 0000
6Fh 0100

Ans2.

0h 3100
1h 7949
2h 2000
3h A231
4h 01E1
5h 0000
6h 0064
7h 2001
8h 0000
9h 0200
Ah 0000
Bh 0000
Ch 0000
Dh 401F
Eh 0C5F
Fh 3000
10h D048
11h 0002
12h 0000
13h 0040
14h 29C7
15h 0000
16h 0000
17h 0040
18h 6B50
19h 4444
1Ah 0002
1Bh 0000
1Ch 0000
1Dh 0000
1Eh 0002
1Fh 0000
32h 00D3
6Eh 0000
6Fh 0100

Ans3.

I confirmed no other straps are placed except for RX_CTRL.

Best Regards,

Ryo

Hi Ryo,

Upon further review of the schematic, I noticed an external clock source is being used. What is the voltage level of the clock?

Thank you,

Nikhil

Hi Nikhil,

Voltage level of the clock :

  Vh = 1.77V

  Vl = 0.05V

Designed with reference to p111 (9.2.1.2 Clock In (XI) Recomendation) in the data sheet.

show attached file :

 /cfs-file/__key/communityserver-discussions-components-files/138/Clock_5F00_Level.pptx  

Best Regards,

Ryo

Hi Ryo,

We are looking into this issue and will provide feedback by Thursday.

Thank you,

Nikhil

Hi Ryo,

This is a difficult problem to debug as the link drop is intermittent, link recovers automatically and data transfer resumes, and this is only seen once every few hours, it is not repeatable. It is additionally more difficult as we can't obtain a register dump during the link-down state. In terms of causes of a link-down event, there could be several. This could be a signal quality issue, a clock issue, etc. Possible sources of SI issues include but aren't limited to long traces, differential traces incorrectly impedance controlled or incorrectly length matched, crosstalk, long cables, or connector issues. I currently do not see any issues with the schematic or with the register dump, which can be confirmed by normal data transfer during the time the register dump was taken.

Does the clock source fit the requirements highlighted by Section 9.2.1.2 in the datasheet?

Are you able to share a layout?

Thank you,

Nikhil

Hi Nikhil,

I think that clock source fit the requirement.

Clock source specification and Layout :
See the following attachment

/cfs-file/__key/communityserver-discussions-components-files/138/Schamatic_5F00_Layout3.pdf

In normal operation, the FLD function is turned off,
Due to debugging, when FLD is enabled, link up and down are repeated within 1 second.
wirte 0x002d [4: 0] = 0x1f
read 0x002d [12: 8] = 5'b00110
MLT3 Errors and SNR level is active

This only happens for certain link partners.
The evaluation board for DP83867IR happens as well.

From this result, we believe that the signal quality of the input signal is the cause.

Is it possible that the same factor (MLT3 Errors and SNR level) causes the link to go down once every few hours when FLD is disabled?

Best Regards,

Ryo

Hi Ryo,

We are looking into this issue and will provide feedback by Monday.

Thank you,

Nikhil

Hi Ryo,

Using the FLD feature it looks like you have narrowed this down to an SNR and MLT3 issue. Again this can be caused by lossy cables or connectors, or non-idealities in layout such as noise or coupling in MDI signals or incorrect differential controlled impedance in the MDI traces. Are you able to share a PCB layout at this time?

Upon further review of the schematic, the supply pin decoupling strategy may need to be updated. Each supply pin should have a 0.1 uF and 1 uF capacitor close to the pin and each supply should additionally have a 10 nF and 10 uF cap. Please refer to Figure 37 in the datasheet. Supply noise may be causing an SNR issue.

Thank you,

Nikhil

Hi Nikhil,

It can be provided.
Please tell us your desired data format and the area you want to refer to.
Layout of each layer around the PHY, etc.

I Consider that supply pin decoupling strategy.

Best Regards,

Ryo.

Hi Ryo,

If possible, please provide the layout design files to be viewed. If these cannot be share publicly, you may share via private message. I have sent a request to connect. I would like to review net names and trace lengths/properties if possible. At minimum please share searchable, schematic, layout, and assembly drawings so I can map components on the schematic to the placement in layout.

In the mean-time, please try the recommended decoupling strategy.

Thank you,

Nikhil