This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

HD3SS3220: UFP, what voltage level on CC1 and CC2?

Intellectual 265 points

Replies: 26

Views: 215

Part Number: HD3SS3220

Hi,

I'm trying to debug a design that doesn't seem to be working.

What voltage level should I see on CC1 and CC2 when the cable is plugged in in both orientations? I have two board built and both work differently.

The design is self powered and thus does not take any power from VBUS. I read (somewhere) that there was a minimum capacitance retirement for the VBUS line in the USB spec, so I added 2 x 22uF caps to the design. This meant that when the cable was removed the voltage on VBUS fell very slowly. For now I have fitted a 10k resistor in parallel with one of the 22uF capacitors. What is recommended for capacitance on VBUS if the device takes no power from the upstream device?

Thanks,

Graham

  • I have attached the schematic if somebody could please review it?

    Type C To Ethernet 1.pdf

  • In reply to Graham North1:

    you design is UPF (port is low)

    For CC voltage, the side connected will go from low to high, the other side will keep low. But the real high voltage is depends on current mode, pls check CC volta e on page 6 of datasheet.

    For Vbus voltage, DFP require big Cap like 150uf, but UFP don't need big cap.

    For schematic, lower the cap value for supply and add a cap on ENMUX pin to VDD33

  • In reply to Brian Zhou:

    Hi Brian,

    Thank you for your reply.

    On one of my boards CC1 was ~0.4V and CC2 0V with the cable plugged in one way up, when the cable was plugged in the other way up CC1 was 0V and CC2 was ~5V. What could cause that? 

    Which cap value do you suggest needs lowering? The one on VBus? What would you recommend?

    What does a cap on ENMUX do? I don't see it mentioned in any documentation. What value should it be?

    Thanks,

    Graham

  • In reply to Graham North1:

    what kind of cable ? type-c to type-c?

    C15 for VDD5  and C44 C49 for Vbus all need to lower.

    ENMUX needs to hold high before VDD5 and VCC33 stable , you can start with 2.2uf. take a waveform with VDD5,VCC33 and ENMUX

  • In reply to Brian Zhou:

    Thank you for your reply.

    USB Type-C to Type-A.

    Can you tell me why C15 needs to be lower? Do you have a value or can you tell me how I can test? Is it a power sequencing thing?

    Any recommended value for VBus?

    I have tied ENMUX directly to GND, so I don't think a cap will help? Do I need to change the enable circuitry? Is there a spec?

    Thanks,

    Graham

  • In reply to Graham North1:

    Are you talking about EN_MUX or EN_CC?

    What is the recommended circuit for connecting them?

    Thanks,

    Graham

  • In reply to Graham North1:

    Hi Brian,

    Do you have any more feedback to help us please?

    Thanks,

    Graham

  • In reply to Graham North1:

  • In reply to Brian Zhou:

    for type-c  to A cable, A5 is connected to 5v though 56k pullup. B is floating that's why you got 5v on one side.

    For EN_MUX, there is a weak pullup, but may not enough if supply ramp up too slow. 

    So other than cc voltage question, any functional issue?

  • In reply to Brian Zhou:

    Hi Brian,

    Thanks for the reply. Did you try to attach a picture or something before the last reply, I can't see it, it shows as an error.

    Page 18 of the datasheet shows the requirement to hold off enabling the ENn_CC pin until the power supply rails have stabilised, is this also a requirement for ENn_MUX too?

    What happens if this delay on the enable pins does not happen? Does the chip not work or is it damaged?

    Do you have a recommended circuit to control the enable pins?

    Can the enable pins be tied together and held high for several seconds after the power rails come up?

    If the requirement for the 3V3 rail to turn off before the 5V rail can not be met does that damage the chip? Is there a drawing for the timing requirements for this?

    I've seen conflicting advice on pulling up the DIR pin. Should it be pulled up to 3V3 or 5V? If it is not used in the design can the pull up resistor be omitted?

    Thanks,

    Graham

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.