DS90UB913A-Q1: DS09UB913A-914A communication problem

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Replies: 7

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Part Number: DS90UB913A-Q1

Hello team, 

About DS90UB913/914, my camera data isn't correctly sent. Could you please help me to address this issue?

Please find my waveform from the internal link here.

The image sensor PCLK is designed at 96MHz.
When the serdes is communicating, the PCLK of deserializer breaks up as shown in waveform #2.
The jitter spec of the image sensor is 600ps, so I don't think the jitter should be the cause.
My customer has experience that the serdes worked with VDDIO=3.3V in another application.
In this use case, VDDIO is 1.8V. My customer set 0x01[4] as 0 to set to 1.8V mode, but the problem was not solved.
Is there any missing register setting specifically for VDDIO=1.8V?
Also, My customer realized that the deseralizer's PLL is locking. Could you please let me know the possible cause of the PLL locking?



7 Replies

  • Hi Itoh

    the 1.8V design is correct. from the waveform it sounds it has toggling in lock pin, when LOCK is high 914a should have data output, is it correct in your case?

    if yes, now your issue is why 914a reports unlock with "low level' in LOCK pin.

    this is one high speed serial link design consideration, pls check:

    1. 913a ref. clock spec.: pls follow up the d/s spec. (including test condition), the 600ps is over spec. but pls double confirm if the test condition is same as d/s request?

    2. cable/connector, we have one app. under the link of ub914a product in www.ti.com

    best regarsd,


  • In reply to Junqiang Shi:

    Hello Steven-san,

    Thank you for your suggestion.

    As you mentioned, my customer's new design has additional B-to-B connectors.

    Also, the impedance doesn't meet +/- 5% tolerance.

    Do you think these could be the potential cause for low LOCK pin?

    Could you let me know the condition which LOCK pin goes low while PDB, OEN, OSS are all "1"? (Probably it is not covered in Table 5 on the DS)

    Could you help me to suggest solution to address this issue? (e.g. register setting )



  • In reply to Kazuki Itoh:

    Hello Kazuki-san,

    You mentioned that the channel design does not meet the impedance tolerance? Do you have data regarding the channel characteristics between the 913A and 914A to share? Is this 913Q/914Q or 913A/914A? Also are you using PCLK from imager mode or external oscillator mode? Also can you please share the schematics for review?

    Best Regards,


  • In reply to Casey McCrea:

    Hi Casey-san,

    OK, I'll clarify that and get back to you later.

    One more thing, my customer tried another sensor with longer negative time and found that the communication gets better.

    Do you happen to know if there's VSYNC negative time limitation for stable serdes communication?



  • In reply to Kazuki Itoh:


    yes, the camera also would impact the link jitter budget as serial transmitter, such as refer clock jitter, on-board noise etc., so this is expected and we can more confidence that this is link margin design issue. pls make sure the camera output jitter spec. based on ds90ub933 output spec.



  • In reply to Junqiang Shi:

    Hello Steven-san,

    I'm using it under the following conditions:

    Device: 913Q / 914Q
    Mode: PCLK mode (Imager mode), 10bit mode
    PCLK frequency: 96MHz (Rise / Fall time = 1ns)
    Cable: Differential impedance 100Ω ± 10% (400mm)

    We were also able to improve by changing to External Oscillator mode.
    So, do you understand the following?

    1) Is there a regulation for PCLK jitter?(0.1T?)
    2) Is there a relationship between cable / connector impedance and PCLK jitter?
    3) Is the rise / fall time "MIN = 0.5T, NOM = 2.5T, MAX = 0.3T"?


  • In reply to user4316494:

    Hi Kato-san,

    913Q/914Q d/s are not updated, you can refer to 913a/914a on the jitter spec. request, this is <=0.3UI (1UI is equal to high speed serial bit width).


    for the 2nd question, generally this is one system issue as video data is transmitted from ser. to de-ser through cable/connector/PCB trace etc., any factor would impact the link margin, the higher PCLK freq. means the link need higher jitter request and channel loss etc.,so for the high PCLK freq., the system design is more challenging.