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SN65DSI84: 0x18 CSR Bit

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Part Number: SN65DSI84

Hi team,

Good day.

The datasheet Table 7-8. CSR Bit Field Definitions – LVDS Registers 0x18 address bits 2 and 3 states the following:

Bit3: 1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled
Bit2: 0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default)

Can you please clarify if this is a typographical error and should be as follows?

Bit3: 1 – Force 24bpp; LVDS channel A lane 4 (A_Y3P/N) is enabled
Bit2: 0 – Force 18bpp; LVDS channel B lane 4 (B_Y3P/N) is disabled (default)


Regards,
Carlo