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DP83TC811R-Q1: DP83TC811

JAY SHI
Prodigy 90 points
Part Number: DP83TC811R-Q1
Other Parts Discussed in Thread: DP83TC811

I use the RGMII interface of NXP LS1043A to connect DP83TC811, receiving is OK, but there is something wrong with sending. MAC terminal provides 125M clock for RGMII gigabit, while PHY terminal provides 25M and 2.5m sending clock for 100 megabit and 10 megabit

  • 0
    TI__Expert 5425 points

    Hi Jay,

    1. Can you elaborate on which side has trouble sending? Is there an issue with the PHY sending packets, or is the issue with the MAC sending packets? Which pins are not working?
    2. Can you check if you are seeing a 25 MHz clock signal on the CLK_OUT pin?
    3. Can you provide a schematic? If you cannot provide it publicly on E2E, you can email it to me.

    Regards,

    Adrian Kam

  • 0 in reply to Adrian Kam
    Prodigy 90 points

    This design has three clock, ref_clk tx_clk and rx_clk ref_clk consists of phy or external clock source to provide 1043, only for 1043 is 125 m, and TI the phy is 100 m, the output clock is 25 m, unable to supply 1043 use, we use the independence of external clock, while tx_clk and rx_clk is to send and receive data synchronization for RGMII interface, rx_clk must be generated by the phy chip, tx_clk depends,If it is working in the phy 1000 M, 125 M by 1043 side to send the clock, gigabit are generated by the phy chip under 25 M (MB) or 2.5 M clock (10 million), you said the delay means tx_clk and rx_clk and temporal relationship between sending and receiving data, and the reference clock has nothing to do, this can be adjusted in phy or 1043, the question now is whether the phy chip after the connection is established, rx_clk is 25 M, 1043 correctly to receive data, and tx_clk is 2.5 M,1043 cannot correctly send data to the opposite end. TX_CLK and RX_CLK are both generated by PHY chip. Now I want to find out under what circumstances will PHY chip produce different sending and receiving clocks

  • 0 in reply to JAY SHI
    Prodigy 90 points

    The sending clock is only 2.5MHz, the receiving direction is normal, and the receiving clock is 25MHz. After capturing the packet, it is found that the network packet can be received normally

  • 0 in reply to JAY SHI
    TI__Expert 5425 points

    Hi Jay,

    In RGMII mode, TX_CLK is not generated from the PHY. It has to be sourced from the processor. As a result, the 2.5MHz clock you are seeing on TX_CLK pin is probably coming from the processor. This needs to be changed to a 25MHz clock.

    Let me know if this fixes your issue. If not, could you upload your schematic again, as it does not seem to be loading on the thread? You can also find my email on my E2E profile and email me the schematic. 

    Regards,

    Adrian Kam