SN65DSI86: The display screen is completely black when the resolution is 3840 * 1080 60 fps in dual DSI to DP mode.

Siquan

Do you have the panel EDID information you can share? 

Can you dump out the other status registers from 0xF0 to 0xF8?

Have you checked the setup and hold timing on the DSI interface to make sure they are meeting the DSI86 requirement?

Thanks

David

Hi David,

Do you have the panel EDID information you can share?

The EDID information is as follows.

EDID:
00ffffffffffff004a8b1b1a01010101
311d0104a50000782aee91a3544c9926
0f5054210800d1c0a9c08bc081c061c0
59c04bc03bc0023a801871382d40582c
450058c31000001ea26c0018f1382d40
2c584500ffff0000001e000000fc0057
435320446973706c61790a20274a0098
a1002a4030701300ffff0000001e01b1
02030bc023097f078301000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
000000000000000000000000000000fa
_MUTTER_PRESENTATION_OUTPUT: 0
HDCP Content Type: HDCP Type0
supported: HDCP Type0, HDCP Type1
Content Protection: Undesired
supported: Undesired, Desired, Enabled
max bpc: 12
range: (6, 12)
Broadcast RGB: Automatic
supported: Automatic, Full, Limited 16:235
audio: auto
supported: force-dvi, off, auto, on
link-status: Good
supported: Good, Bad
CONNECTOR_ID: 107
supported: 107
non-desktop: 0
range: (0, 1)
1920x1080 (0x48) 148.500MHz +HSync +VSync *current +preferred
h: width 1920 start 2008 end 2052 total 2200 skew 0 clock 67.50KHz
v: height 1080 start 1084 end 1089 total 1125 clock 60.00Hz
3840x1080 (0x256) 278.100MHz +HSync +VSync
h: width 3840 start 3884 end 3972 total 4120 skew 0 clock 67.50KHz
v: height 1080 start 1084 end 1089 total 1125 clock 60.00Hz
2560x1024 (0x257) 189.830MHz +HSync +VSync
h: width 2560 start 2608 end 2720 total 2968 skew 0 clock 63.96KHz
v: height 1024 start 1025 end 1028 total 1066 clock 60.00Hz
1920x1080 (0x56) 148.352MHz +HSync +VSync
h: width 1920 start 2008 end 2052 total 2200 skew 0 clock 67.43KHz
v: height 1080 start 1084 end 1089 total 1125 clock 59.94Hz

Can you dump out the other status registers from 0xF0 to 0xF8?

Here are the register values for when error happened.

addr: 0xf0 data : 0x0
addr: 0xf1 data : 0x0
addr: 0xf2 data : 0x0
addr: 0xf3 data : 0x0
addr: 0xf4 data : 0x1
addr: 0xf5 data : 0x0
addr: 0xf6 data : 0xc0
addr: 0xf7 data : 0x0
addr: 0xf8 data : 0x1
addr: 0xf9 data : 0x0

Have you checked the setup and hold timing on the DSI interface to make sure they are meeting the DSI86 requirement?

Now we have some difficulties in measuring the signal.

For dual DSI mode, should the routing of DSI0 and DSI1 be equal on hardware?

Thanks for the quick response.

Siquan

Siquan

Do you want me to review your board layout file?

The DSI0 and DSI1 should keep lengths to within 5 mils of each other.

Address 0xF6 thru 0xF7 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers. I generated the DSI86 register programming value based on the provided EDID, can you please double check to see if the registers are being programmed correctly?

<aardvark> 
<configure i2c=1 spi=1 gpio=0 tpower=1 pullups=0/> 
<i2c_bitrate khz=100/> 

======ASSR RW control  ====== 
<i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/> 
<i2c_write addr=0x2D count=1 radix=16> 16 1 </i2c_write>/> 
<i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/> 

======REFCLK Frequency  ====== 
<i2c_write addr=0x2D count=1 radix=16> 0A 2 </i2c_write>/> 

======DSI Mode  ====== 
<i2c_write addr=0x2D count=1 radix=16> 10 00 </i2c_write>/> 

======DSIA Clock  ====== 
<i2c_write addr=0x2D count=1 radix=16> 12 21 </i2c_write>/> 

======DSIB Clock  ====== 
<i2c_write addr=0x2D count=1 radix=16> 13 21 </i2c_write>/> 

======DP Datarate  ====== 
<i2c_write addr=0x2D count=1 radix=16> 94 80 </i2c_write>/> 

======Enable PLL  ====== 
<i2c_write addr=0x2D count=1 radix=16> 0D 1 </i2c_write> <sleep ms=10/> 

======Enable enhanced frame  in DSI86  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5A 4 </i2c_write>/> 

======Number of DP lanes  ====== 
<i2c_write addr=0x2D count=1 radix=16> 93 20 </i2c_write>/> 

======Start Semi-Auto Link Training  ====== 
<i2c_write addr=0x2D count=1 radix=16> 96 0A </i2c_write> <sleep ms=20/> 

======CHA Active Line Length  ====== 
<i2c_write addr=0x2D count=2 radix=16> 20 C0 03 </i2c_write>/> 

======CHB Active Line Length  ====== 
<i2c_write addr=0x2D count=2 radix=16> 22 C0 03 </i2c_write>/> 

======Vertical Active Size   ====== 
<i2c_write addr=0x2D count=2 radix=16> 24 38 04 </i2c_write>/> 

======Horizontal Pulse Width   ====== 
<i2c_write addr=0x2D count=2 radix=16> 2C 2C 00 </i2c_write>/> 

======Vertical Pulse Width   ====== 
<i2c_write addr=0x2D count=2 radix=16> 30 05 00 </i2c_write>/> 

======HBP   ====== 
<i2c_write addr=0x2D count=1 radix=16> 34 94 </i2c_write>/> 

======VBP   ====== 
<i2c_write addr=0x2D count=1 radix=16> 36 24 </i2c_write>/> 

===== HFP  ====== 
<i2c_write addr=0x2D count=1 radix=16> 38 58 </i2c_write>/> 

===== VFP  ====== 
<i2c_write addr=0x2D count=1 radix=16> 3A 04 </i2c_write>/> 

===== DP-18BPP Disable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5B 0 </i2c_write>/> 

===== Color Bar Enable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 3C 02 </i2c_write>/> 

===== Enhanced Frame, and Vstream Enable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5A 0C </i2c_write>/> 

</aardvark> 

Thanks

David

Hi,David

3840x1080 (0x256) 278.100MHz +HSync +VSync
h: width 3840 start 3884 end 3972 total 4120 skew 0 clock 67.50KHz
v: height 1080 start 1084 end 1089 total 1125 clock 60.00Hz

Here are registers dump from 0x20 thru 0x3A, I think these registers have been programmed correctly.

addr: 0x20 data : 0x80
addr: 0x21 data : 0x7
addr: 0x22 data : 0x80
addr: 0x23 data : 0x7
addr: 0x24 data : 0x38
addr: 0x25 data : 0x4
addr: 0x26 data : 0x0
addr: 0x27 data : 0x0
addr: 0x28 data : 0x0
addr: 0x29 data : 0x0
addr: 0x2a data : 0x0
addr: 0x2b data : 0x0
addr: 0x2c data : 0x58
addr: 0x2d data : 0x80
addr: 0x2e data : 0x0
addr: 0x2f data : 0x0
addr: 0x30 data : 0x5
addr: 0x31 data : 0x80
addr: 0x32 data : 0x0
addr: 0x33 data : 0x0
addr: 0x34 data : 0x94
addr: 0x35 data : 0x0
addr: 0x36 data : 0x24
addr: 0x37 data : 0x0
addr: 0x38 data : 0x2c
addr: 0x39 data : 0x0
addr: 0x3a data : 0x4

But Semi-Auto Link Training successed only when DP_DATARATE was 1.62 Gbps,Maybe that's the problem.How to make training successful when other DATARATE was set?

Our layout does not meet this requirement "The DSI0 and DSI1 should keep lengths to within 5 mils of each other". We try to add flywire to meet requirement,but nothing changes.

Lengths of DSI on layout are here in this file.Please check and give some suggestions.

DSI_issue.xlsx

Thanks

Siquan

Siquan

The EDID info provided in register 0x36 and 0x37 is 0x2 and 0x3A, which is 3A02 or 148.5MHz. For 148.5MHz, you don't need dual DSI mode, single DSI mode is sufficient. 

The EDID also indicated the Horizontal Active is only 1920 pixel, not 3840 pixel. So it seems that there is a discrepancy between the EDID and your resolution.

If you are using the dual DSI mode, then CHA_ACTIVE_LINE_LENGTH_LOW and CHA_ACTIVE_LINE_LENGTH_HIGH controls only the number of odd pixels in the active horizontal line that are received on DSI channel A. When configured for Dual DSI inputs in Left/Right mode, this field controls only the number of left pixels in the active horizontal line that are received on DSI channel, but not the entire horizontal pixel lane. 

Channel B controls the number of even pixels  in the active horizontal line that are received on DSI channel B or right pixels in the active horizontal line that are received on DSI channel B.

Thanks

David

Hi,David

The EDID info are from screen splitter. Screen splitter can support Horizontal Active 3084 pixel and we need this resolution. So CHA_ACTIVE_LINE_LENGTH_LOW and CHA_ACTIVE_LINE_LENGTH_HIGH is 0x80 and 0x7,which is 0x780 or 1920 when configured for Dual inputs in Left/Right mode.

Thanks

Siquan

Siquan

Can you enable the DSI86 color bar and see if it works? 

For enabling of the color bar mode, register 0x3C need to be set to be 0x1x. ‘1’ is to enable the color bar and ‘x’ is to select different color bar pattern.

Thanks

David

Hi，David

It works correctly when enable color bar. 

Thanks

Siquan

Siquan

With the color bar working correctly, the DSI86 eDP interface is working correctly. 

Is there a way you can improve the DSI86 DSI interface connection? If you change the DSI_EQ value in register 0x11, does that help?

Thanks

David

Hi,David

I still get 0x0c in register 0xf6 when DSI_EQ value changed.

Thanks

Siquan

Siquan

If you look at the error message in register 0xF6, 0xC0 would indicate

VIDEO_WIDTH_PROG_ERR. This field is set whenever the video parameters define more bytes of pixel data than can be transferred in the allotted video portion of the line time.

LOSS_OF_DP_SYNC_LOCK_ERR. This field is set whenever the DP sync generator has lost lock with the DSI sync stream.

Can you map the HSYNC output to the GPIO pin and then use a scope to probe the GPIO pin to see if it meets the panel requirements? To map the HSYNC to GPIO3, please set Register 0x5F to 0x20. HSYNC frequency = Pixel Clock / Htotal, this should be the panel requirement. 

Thanks

David