DS90UB662-Q1: frame synchronization signal

Jiawei Hu1

Expert 4365 points

Part Number: DS90UB662-Q1

Hi team,

I have several questions about UB633A and UB662, could you kindly answer below questions?

What is the maximum error when the four-channel frame synchronization signal is input to the four cameras?
If 633 uses electrostatic diode, where should the electrostatic diode be placed, near the Fkara terminal or the Ser PIN pin terminal?

Thanks for your help!

Jiawei

over 3 years ago

0 Jiashow Ho over 3 years ago

TI__Genius 11340 points

Hi Jiawei,

1. You shouldn't see errors with the framesync if it's configured properly.

2. Please give me a couple days to find this information out.

Best,

Jiashow

0 Jiashow Ho over 3 years ago in reply to Jiashow Ho

TI__Genius 11340 points

Hi Jiawei,

For #2, typically it should be near the connector since that is likely where the ESD will originate from. It is better to suppress it near the source to keep its effects as far from the protected IC as possible.

0 Jiawei Hu1 over 3 years ago in reply to Jiashow Ho

TI__Expert 4365 points

Hi Jiashow,

Thanks for your reply, maybe my question is not clear. For #1, what I want to know is the time of the 'limited skew'?

I have another question is that if the jitter (PCLK from imager mode) is higher than 0.45UI (MAX jitter), what can I do to improve jitter?

Jiawei

0 Jiashow Ho over 3 years ago in reply to Jiawei Hu1

TI__Genius 11340 points

Hi Jiawei,

Please give me some time to look into if we have skew data.

As for your question on jitter, usually you can improve jitter by using a better cable, a shorter cable, a PCLK source with less jitter, good impedance control on the board.

Best,

Jiashow

Interface

Interface forum

DS90UB662-Q1: frame synchronization signal