Other Parts Discussed in Thread: AM26LS31
Team,
can you help with the below from a customer?
We’ve had a supplier make a mistake and if I’m reading the datasheet I can see how they may have made the mistake BUT the supplier should have looked at the absolute max numbers.
The part number off concern is SN65LVDT34 with is an LVDS receiver with integrated termination.
At first glance I thought the datasheet had a typo listing the AM26LS32 in the pin compatibility list, but thought I’d do a “what if” in the event the author was thinking outside the box.
So please bear with me on my thoughts while I introduce a EIA/422 line driver because I’m wondering if under certain circumstances (low-speed and closed/common ground system) the SN65LVDT receiver could be paired with a AM26LS31 driver.
In the datasheet for the LVDS receiver lists that its pin compatible with a EIA/422 receiver
I submitted a question concerning the power dissipation for the integrated 110 ohm resistor for the SN65LVDT34 and the TI reply was 444mW.
Generally we’d pair the AM26LS32 with a AM26LS31 in our system designs.
The AM26LS31 datasheet doesn’t spec a max voltage swing, just a minimum voltage (2.5-0.5V = 2V). However we’ve measured in the lab 3.5V, but assume worse case of 5V just for fun, but maybe the standard allows up to 6 to 7V (we are closed system, solid grounding so the common mode swing would not exceed 5V or whatever Vcc to the chip is) .
In worse case conditions the power dissipated through the resistor would be 227mW (P=V^2 / R= 5V^2 / 110ohm). So seems like I have plenty margin on the power budget there.
However a 5V differential swing definitely exceeds the voltage range Va-Vb ratings of 1V for the SN65LVDT34 and even exceeds the Vid [LVDS] rating of 3V max.
The TTL input max voltage of 5V is not exceeded at the SN65LVDT34 device if driven by AM26LS31 with Vcc of 5V.
The input stage at the attenuation network (page 3 of the datasheet) of the SN65LVDT34 presents as high impedance such that the majority of the current flows through the integrated resistor which mathematically appears to have margin.
So circuit-wise I can’t see what/if anything would be electrically overstressed. Is that a true statement? What am I missing?
The only thing that I could see being an issue is the data rate because of the higher-differential voltage swing (device characterized for Mbps rate at low diff voltage swing). Is that a true statement? If so, the signals we have on this interface are very slow (i.e. control signals, not data signals) and that might explain why we never saw any issues.
Thoughts? What am I missing or did the TI author really think outside the box here?