DP83867CRRGZR, has 4 configurable MDIO address bits. When addressing the device, is the non programmable address bit, PHY_ADD[4], assumed to be 0 or 1?
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DP83867CRRGZR, has 4 configurable MDIO address bits. When addressing the device, is the non programmable address bit, PHY_ADD[4], assumed to be 0 or 1?
Hi Gregory,
PHY_ADD[4] is assumed to be 0, as the DP83867CR supports PHY addresses from 0 to 16.
Regards,
Adrian Kam