TLK10232EVM: BER Testing on Channel B HS side

MADHUSUDANA RAO KOTHARI

Part Number: TLK10232EVM
Other Parts Discussed in Thread: TLK10232

Hi,

We are trying measure the BER in the loop back mode using TLK10232EVM board on Channel B HS side. We are not getting error rate of the channel correctly. It means we are geeting NaN in open and close loop cases . Screen shot FYI.

over 3 years ago

0 Drew Miller1 over 3 years ago

TI__Mastermind 18841 points

Hi,

It appears that your screenshot did not upload correctly to the forum. Could you please try to re-attach it in order to help us resolve your BER issue.

Thanks,

Drew Miller

HSSC Applications Engineer

0 MADHUSUDANA RAO KOTHARI over 3 years ago in reply to Drew Miller1

Prodigy 50 points

Screen shot pasted FYI.

Best regards,

Madhusudana

0 Rodrigo Natal over 3 years ago in reply to MADHUSUDANA RAO KOTHARI

TI__Mastermind 19135 points

Hi,

Please confirm that your Line Rate and Reference Clock selection and implementation for low-speed and high-speed sides are correct. Refer to datasheet.

Also, please check that your configuration for the following pins agrees with datasheet and makes sense for your application case:

ST, MODE_SEL, PRBSEN, RESET_N, TESTEN

You may refer to the application note below for additional debug suggestions.

www.ti.com/.../slla351a.pdf

Thanks,

Rodrigo Natal

HSSC Applications Engineer

0 MADHUSUDANA RAO KOTHARI over 3 years ago in reply to Rodrigo Natal

Prodigy 50 points

Hi,

0 MADHUSUDANA RAO KOTHARI over 3 years ago in reply to Rodrigo Natal

Prodigy 50 points

Hi,

0 MADHUSUDANA RAO KOTHARI over 3 years ago in reply to Rodrigo Natal

Prodigy 50 points

Apologies for delayed response.

We have connected a clock source REFCLK0n and REFCLK0p and observed PLL is locked. We are enabled PRBS also.

But the results of Channel B HS side is still shows NaN.

0 MADHUSUDANA RAO KOTHARI over 3 years ago in reply to Rodrigo Natal

Prodigy 50 points

Hi,

Apologies for delayed response.

We have enabled the setting for internal loop back for all the modes of ST, MODE_SEL, PRBSEN, RESET_N, TESTEN.

We have connected a clock source REFCLK0n and REFCLK0p and observed PLL is locked. We are enabled PRBS also.

But the results of Channel B HS side is still shows NaN.

Can you arrange the step by step procedure along with the required setting for getting BER in CHANNEL B HS side?

or it will be great help if you arrange any video Demo of TLK10232 EVM Board.

Best regards,

Madhusudana

0 Rodrigo Natal over 3 years ago in reply to MADHUSUDANA RAO KOTHARI

TI__Mastermind 19135 points

Hi,

Do you have either a high-speed oscilloscope or BERT available that you can use to measure the 10G data output by TLK channel A to confirm that it looks good?

Thanks,

Rodrigo Natal

Interface

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TLK10232EVM: BER Testing on Channel B HS side