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SN65HVD102: SN65HVD10x TX buffer delay

Part Number: SN65HVD102

Hello Team,

the SN65HVD10x has a driver enable delay that is specified by max. 5us.

We do see that the majority of the device actually have a delay more in the range of 1us but there are very few that are in the range of 3us.

From statistical perspective I would say that the number of devices that will have 5us delay would be less than the typical ones (even if is not specified in datasheet). 

There are some IOLink applications where the message must be sent back within 3.5us and with 3us delay the first bit could be cut out, generating errors.

  • What is influencing the delay of the buffer? (within the 1-5us range)
  • Is it only process variation and temperature or are there other parameters that let it change?

V L+ is also influencing the delay, what does it change internally that let the delay being influenced by L+.

The internal current generators are not referring to internal ref, but to L+

Thanks,

SunSet

  • SunSet,

    Unfortunately I didn't find any statistical data from either simulation or characterization, so it's hard to estimate how the delay is distributed. In one bench measurement consisting 10 devices, the delay varies from about 1.5us to 2.4us with supply and temperature variation. The 3rd factor that was not counted in is process variation. The reason L+ voltage changes the delay is not due to the internal current generator. As L+ decreases, the driver has less headroom to drive the output load. Please let me know if you have any other questions.

    Regards,
    Hao
  • Hello Hao,

    thanks for your feedback.

    SunSet