PCA9557: About I2C behavior in the case where the lock-up

Hey User4030081,

Sorry for the late reply here. I didn't see your response until now when I checked which threads were still 'open.'

"You answered that this is a possibility that the SDA signal will stay low while leaving the FET on the SDA pin ON.
Which of the following does this mean?"
During a bad PoR condition the state machine of the device starts up in an unknown state. In this instance some gates could see logic highs and when they are supposed to see logic lows and vice versa. Because the digital starts up in a unknown state I cannot say with 100% certainty that the device will not start up in a latched state and unlatch itself.

I can say that there are two ways which should always fix this:
1) Do a GOOD power cycle
2) Do a reset on the reset pin

"Please tell me the reason to reset by pulsing 9 to 18 pulses."
This is the I2C recommendation on how to fix a stuck bus. The idea here is the device has missed a clock cycle and latches the bus low (example: device ACKs on the 9th clock pulse but never sees the rising edge to release SDA).

Sending 9 to 18 clock pulses is a way to attempt to fix a stuck bus by trying to reset the device's state machine. In this case, what if our device started up in a state which it thought it was on the 4th clock pulse of a read transaction and the 4th bit was a logic low? The state machine would latch SDA low until it sees a minimum of 5 more clock cycles.

"Please tell me in detail how to reset control."
option1: Do a good PoR
option2: drive reset low and then high again

Thanks,
-Bobby