P82B96: How to calculate the bus delay?

Hello Hisao-san,

I've been looking at this for a while trying to figure out the highlighted portions you pointed out.

The 400ns highlight I believe is a by product that comes from the device's architecture. When you drive low on the S line then release, the bus will hang at the static voltage offset (~800mV) for some time before releasing). This isn't a spec in the datasheet and looks like it is just called out here. I used this device for an I2C to CAN application and found my delay was around 500ns but that included the CAN prop delays. I'm  not sure if the 400ns is a typical value or if it relates to Vcc.

The 490ns time is likely the prop delay from S side to T side then R side to S side plus the cable prop time plus something else?  70ns (fall from S to T sec.7.9) + 250ns (fall from R to S sec.7.9) + 125ns (table's cable delay) = 445ns. It looks like with my calculation, I am missing 45ns to their calculation. This could be attributed to the fall time of the master generating the falling edge and any fall times from the buffer. I suspect the writer of the datasheet may have had this device set up and had scopeshots of this timing.

The 580ns is liking the buffers prop delay plus the cable prop delay. So the same as above: 90ns (s side to T side) +270ns (R side to S side) + 125ns (cable delay) = 485 ns so we're missing 85 ns.

There may have been a equation prior, which allowed the user to plug in system level numbers to approximate these values above.

The 1535 ns comes from 1300 ns plus the 235ns. The 1300ns comes from the I2C spec's clock low minimal time for fast mode.

Thanks,

-Bobby

Hi Bobby,

Thank you for your explanation.

So our understanding is table 1 shows some test results for specific conditions.The area circled in yellow shows the conditions and the area circled in blue shows the measured result. Correct?

Regards,

Uchikoshi