Other Parts Discussed in Thread: USB-2-MDIO
Before doing this, the state of the PHY is that it is working as intended for receiving/sending network packets. I am able to send/receive UDP/TCP packets using the LWIP library. (The micro is STM32F7 if relevant)
I am sending PTP version2 messages using the linux PTPD daemon manpages.debian.org/.../ptpd.8.en.html that acts as a master.
On wireshark, I see that sync messages are being sent periodically.
On the micro side, I use an STM32F7x microcontroller with the DP83640 PHY. I configure the registers in the following order, as suggested by the PHYTER_Software_Development_Guide.pdf, cross referenced with the DP83640 datasheet. I also had a look at PTPControl.c to see how it is done there, I noticed version 1 PTP was used in that example. Using the epl_1588.c library provided, here are the initialisation configurations:
First, 0x2 is written to the PTP_CTRL register, to disable the clock.
PTPClockSetRateAdjustment( pEPL_HANDLE, 0, FALSE, FALSE);
The clock rate adjustment is set to be none, by writing 0 to PTP_RATEL and PTP_RATEH. I believe those are the default values too.
PTPClockSet( pEPL_HANDLE, 1, 0);
Then, the PTP clock is set to be 1 second and 0 nanoseconds.
PTPSetClockConfig (pEPL_HANDLE, CLKOPT_CLK_OUT_EN, 0x0A, 0x00, 8u);
After that, the PTP clock is configured by writing 0x800a to PTP_COC. This represents enabling the CLK_OUT and a divider of 10. 0x8 is written to the PTP_CLKSRC register, to represent the internal 125MHz clock to be used, and 8 ns period.
We enable the clock again.
PTPSetTransmitConfig(pEPL_HANDLE, TXOPT_TS_EN | TXOPT_IPV4_EN, 2, 0, 0);
Here, we write 0x25 (0b100101) to the PTP_TXCFG0 register. This represents enabling IPv4 timestamp TX_IPV4_EN, TX_PTP_VER being 2 and TX_TS_EN being 1.
PTPSetReceiveConfig(pEPL_HANDLE, RXOPT_IP1588_EN0|RXOPT_IP1588_EN1|RXOPT_IP1588_EN2| RXOPT_RX_IPV4_EN|RXOPT_RX_TS_EN|RXOPT_ACC_UDP|RXOPT_ACC_CRC|RXOPT_RX_SLAVE , &rx_cfg_items);
Here, we write 0xf25 to the PTP_RXCFG0 register. This represents RX_SLAVE being 1, IP1588_EN being 0b111, RX_IPV4_EN being 1 and TX_PTP_VER being 2 and RX_TS_EN being 1.
After those configurations, I constantly read the register PTP_STS to see if there is a receive timestamp. If there is, I get it by calling PTPGetReceiveTimestamp.
I am only able to successfully get the PTP timestamps (i.e. PTP_STS implies that there is a receive timestamp) if I run the above startup in debug mode. Specifically, stepping through them one by one, with some pause after the PTPSetClockConfig command. If the startup code is ran without any breakpoints, further reads of PTP_STS always results in 0. I am not sure why this is the case. Maybe the ClockConfig is not done setting up before we enable the PTP clock again?
Problem 2: Assuming I am able to get the timestamps, if I stop the linux PTP master, then restart it, the PHY is never able to get new timestamps.
Does anyone have any ideas?