DP83TC811S-Q1: ESD Clamp & input voltages

Steve Widener

Part Number: DP83TC811S-Q1

Please confirm:

1. The voltage limit on all pins is 4V, does this mean the ESD structure does not clamp the pin to the VDDA or VDDIO rail with a diode-like structure?

2. If so, does this mean that if VDDIO or VDDA are at ground, no significant leakage current will flow into the other I/O pins?

3. The XI clock can be 1.8V level regardless of the VDDIO level (1.8V, 2.5V, 3.3V)

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru** 122988 points

Hello Steve Widener

Thank you for the query.

For question number 3 , please see below

Regarding Question number 1 and the subsequent question,

The 4V rating is for continuous input. The DP83TC811S-Q1 has robust integrated ESD circuitry and offers an ESD sensing architecture.

I will revert back with any additional info i may have.

Regards,

Sreenivasa

0 Steve Widener over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Genius 9575 points

Please advise how much leakage current will flow from the I/O pins to a grounded VDDIO with 3.3V applied to the I/O pin

0 Kallikuppa Sreenivasa over 3 years ago in reply to Steve Widener

TI__Guru** 122988 points

Hello Steve,

We typically spec the maximum input for the IO with respect to VDDIO + 0.3. Let me check availability of setup to check the leakage current and come back

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru** 122988 points

Hello Steve,

We use dual diode for all GPIO pins. Hence, if the pin voltage is higher than the supply, there will be a path for current flow to the supply. This may or may not be damaging based on whether the over voltage condition is transient or static.

We typically spec the maximum input for the IO with respect to VDDIO + 0.3 and the data sheet abs max rating, needs to be updated

Regards,

Sreenivasa

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DP83TC811S-Q1: ESD Clamp & input voltages