DS90UB948-Q1: No output on LVDS signals but everything else looks normal

Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: ALP, DS90UH949-Q1EVM, DS90UH948-Q1EVM

So settings:

-- Link LED is on. We can see through the ALP tool that the Serializer and Deserializer are communicating. We can also see that the serializer is getting an HDMI input video stream.

-- We have also have a matching set up with a serializer and deserializer evaluation (DS90UH949-Q1EVM & DS90UH948-Q1EVM ) board. 

-- We are using the ALP tool to interface with the 949. We are able to see the registers of both the 948 and 949 chips. The registers seem to be the same between our 948 chip and the 948 evaluation set up. 

-- We also see less than 100mA current draw when the deserializer is set. So we believe the LVDS signals are not being driven. We also have scoped these signals and see not data. 

-- We also have the recommended RC circuit on PDB, so that at power up, PDB is delayed. 

  • Another piece of information that I would like to add is:

    When we look at our Evaluation board setup, through the ALP tool, we see the pixel clock of the HDMI to FPD Link is running at ~ 74.4Mhz and the pixel clock of the FPD Link to Deserializer is running at ~71.3Mhz.

    But when we look at our designed board we see the pixel clock of the HDMI to FPD link is running at ~74.4 and the pixel clock of the FPD link to Deserializer is running at ~ 75.1Mhz.

    Could this be an issue or a clue to what could be wrong?

  • Hi John,

    The frequency measured by the ALP tool will have some offset.

    Would you be able to measure the clock output from 948?

    Best Regards,

    Charley Cai