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TLK110: About Reserved bit of SWSCR2 and CDCR register

Part Number: TLK110

Hello,

My customer is asking about Reserved bit.

They face a problem three TLK110s isnt started up.

 They checked power up timing (t1(POR):270ms typ) and rise timing of between PFBOUT(1.55V) and AVDD33 but these timing was no problem.

(They use internal POR.)

They use single supply operation and checked decap capacitor value and voltage at PFBIN/OUT but these was no problem.

 (Question)

They found out the following reserved bit of SWSCR2 and CDCR register are set 1 on problem devices

The normal devices are set 0 correctly. Of Course, They didnt write to reserved bit, and read it only.

(Reserved bit 1 on problem devices)

SWSCR2bit148

CDCRbit6,bit7

 

(1) Are those bit settings related to started up problem?

(2) Why are those bit settings on problem devices?

(3) Are these devices in fail mode? Or should they request to Failure Analysis?

 

Regards,

Tao_2199

  • Hello,

    Are they using crystal or external oscillator?  Have they tried using resetn pin or software reset (register 0x001F) when this issue happens to see if it recovers? We don't have further information on reserved bits but most likely they should be tied to 0.

    --

    Regards,

    Vikram

  • Hello Vikram,

     

    For answer some of your questions:

     (1) Are they using crystal or external oscillator? 

    (Ans)

    External oscillator is used. (External oscillator -> Clock Buffer -> TLK110)

    (2) Have they tried using resetn pin or software reset (register 0x001F) when this issue happens to see if it recovers?

    Reset pin

    -> Reserved bit is recovered correctly (0) and TLK110 is start up correctly.

    Software reset

    -> Reserved bit isnt recovered(1) and TLK110 isnt start up correctly.

    (The problem isn't solved.)

     

    From above result, do you think possible root cause will be power-on reset(POR)?

    If so, do you have any solution and advice?

     

    Regards,

    Tao_2199

  • Hello Tao,

    I suspect that external oscillator is stablizing to 25MHz after the supplies have ramped up. Is toggling resetn after some delay to make sure that oscillator is stable a possible solution?

    --

    Regards,

    Vikram

  • Hello Vikram,

    Thank you for reply.

    I’m asking to my customer external oscillator output stability.

    I have a question.

     

    When the external oscillator is input to Xin after the supplies have ramped up, is CLKOUT output from through Xin ?

     (Is it output right away?)

    Or, will CLKOUT be output after reset released? (Please see below.)

    They confirmed CLKOUT output after reset released(about 750ms after the supplies have ramped up).

     

    Regards,

    Tao_2199

  • Hello Tao,

    For TLK110 I could not find if clkout is gated by reset or not. We need to rely on observation at customer's end for that. But for current issue under debug, they should directly check stability of clock at XI.

    --

    Regards,

    Vikram

  • Hello Vikram,

     

    Sorry for delay.

    My customer confirmed XIN clock signal on each problem TLK110( 2pcs.).

    (Please see attach file. Two captured wave signal plots.)

    It seems that max +3.9V ~ - 0.6V over/under shoot. (ABS spec: +3.8~-0.3V)

    Is there any impact on device?

    Do you think over/under shoot is possible root cause of problem?

     

     

    Regards,

    Tao_2199

  • Hello Tao,

    As mentioned earlier we were looking for the delay between XI stablization and all supply ramping up? Is that already captured? What is the conclusion of that? I suspect XI clock not stablizing before the supply ramping up to be the root-cause.

    Regarding measurement of overshoot and undershoot : are these waveforms captured close to the pins of PHY? (just to be sure that this is not artifact of reflections). If they are at pin, then yes it is a violation of the spec but it may not be the root cause of the above issue. Do you see the same on good boards also?

    -

    Regards,

    Vikram

  • Hello Vikram,

     

    Thank you for comments.

     

    > XI stablizing and all supply ramping up? Is that already captured?

    > What is the conclusion of that? I suspect XI clock not stablizing before the supply ramping up to be the root-cause.

     

    (Ans.)

    Please see below captured wave signal.

    The external clock is input at same timing of power up (3.3V).

      

     

    My customer use for only 3.3 V single power and use internal LDO for 1.55V power.

    Also, they confirmed the supply ramping up of 3.3V and 1.55V is same timing

     

    And they reviewed the measurement points and measured XI clock again.

    ( Please see below captured wave signal.)

    It seems that over/under shoot are within ABS spec:(+3.8~-0.3V).

    They confirmed above captured wave signal is same on good board also.

     

    From above result, I think possible root cause may be power-on reset(POR).

    Could you please give some comment or advice?

     

    Regards,

    Tao_2199

  • Hello Tao,

    Can they pre-pone stablization of XI clock source such that it can stablize before power supply ramps up? Do they have control over the reset pin of the PHY? Can they try toggling reset after power up and see if the issue recovers?

    --

    Regards,

    Vikram