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DP83867E: DP83867 review schematic diagram

kevin.huang_FJXM
Expert 2925 points
Part Number: DP83867E

Attached is the dp83867 application circuit I drew. Please help me check if there are any mistakes in the circuit design. Thank you!

I want to configure this chip to sgmii mode, set the transmission rate to 10 / 100 / 1000, PHY address to 0000

The main questions are as follows:

1. Several strap pins default the pull-up and pull-down of internal resistance;

2. Whether there is a STARP pin missing configuration;

3. The power supply of the chip is as follows:

1.0V power supply: continuous power supply current of 300mA;

2.5V power supply: the continuous power supply current is 150mA;

1.8V power supply: 1.8V power supply (50mA) output by 4G module

  • 0
    TI__Genius 16025 points

    Hello,

    I will have a look at the shared schematic and will revert back in a few days. What are those inductors and capacitors for on td_* pins?

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Expert 2925 points

    hi Vikram:

    Customer response：

    The magnetic beads and capacitors connected to the TD * output pin are designed to improve the signal immunity. There was a project without these magnetic beads and capacitors before, and the BCI test failed

  • 0 in reply to kevin.huang_FJXM
    TI__Genius 16025 points

    Here are the schematic review comments:

    1. Each of supply pins should have dedicated 1uF and 100nF decap (pins 19,30,41,3,9,6,24,31,42,13,48).

    2. Board ground and connector ground should be separated by 1Mohm resistor in parallel with 4.7nF cap.

    3. AC copuling caps on the Sgmii lines should be placed close to the Sgmii transmitters.

    4. Pins 20,21,22,23 (JTAG) can be left unconnected if not used.

    5. Is it possible to use ESD devices connected between each trace and ground?

    --

    Regards,

    Vikram