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SN65DSI83: REFCLK level translator

Part Number: SN65DSI83
Other Parts Discussed in Thread: TXS0102, SN74AUC1G17, SN74AUC1G125, LSF0101, LSF0102

Hi,

I have a separate clock source which is at 3.3V. Clock can be 25MHz to 154MHz. I wish to use this clock source to feed the REFCLK input of the SN65DSI83.

Could you please recommend a voltage translator that can convert 3.3V to 1.8V at this high speed, suitable for the SN65DSI83? I'd prefer unidirectional, single channel part.

I considered TXS0102 but I don't think that is fast enough.

Thank you very much in advance

Kind regards

Navin

  • Hi Navin,

    I'll move this thread to the logic section for suggestions on voltage translators. 

    Regards,

    I.K. 

  • Hey Navin,

    Take a look at the LSF0101. It's a single channel translator. Similar to the TXS, it will be open drain but can also be used for pushpull applications as well if needed. but this will be auto-bidirectional rather than unidirectional as you wanted but i'm not sure how much that will matter. There isn't directionality pin to it so it's just a 6 pin device.
    Here's some more information on this: 
    https://www.ti.com/lit/an/slva675b/slva675b.pdf 
    You'll see in the app note, in section 5.4 it mentions "The LSF family can translate up at 100 MHz and down at 200 MHz with reasonably good signal integrity". 

    There's also a series of LSF videos to help better understand the family as well:
    https://training.ti.com/translation-basics-lsf-family

    I recommend watching all the videos but specifically there is a Down Translation with the LSF Family video may be of interest. 

    Hope this helps,
    Rami

  • Hi Rami

    Thanks for the suggestion, is the LSF faster than the TXS? can I use the LSF in place of the TXS if I want to pass I2C through?

    Below is the spec for the REFCLK for SN65DSI83 (page 10 of this datasheet SN65DSI83)

    I assume my circuit will be like below. I will not be using pull-up resistors on A1/B1 because B1 is connected to push-pull output on MPU, and A1 is connected to SN65DSI83 REFCLK pin whose max input current is 30uA.

    Vref_B needs to be > Vref_A + 0.8V, so Vref_B = 3.3V and Vref_A = 1.8V. That means my VGATE is 3.3V.

     

    From section 6.7 of the LFS0101 datasheet, Rise/fall times at 50pF load capacitance is >1ns which is out of spec of the SN65DSI83 REFCLK. It is unlikely that the load capacitance will be 50pF, but I don't know what the input capacitance of the SN65DSI83 REFCLK is because it is not on the datasheet. Will IK Aniyam be able to help with that information? 

    Please let me know if this is ok, or do I need a faster voltage translator?

    Thank you very much in advance

    Navin

  • Navin,

    I'd recommend using an active translator instead then. The rise/fall times are fast (<1ns) and you'd have more room to budge on the bandwidth. The input can support up to 3.6V while the supply is between 0.8 to 2.7V.  The SN74AUC1G125 or the SN74AUC1G17 would work. So your Vcc would be the 1.8V and you'd drive the 3.6V into the input A. The output, Y, of the AUC would go to the REFCLK. The G125 has an enable pin while the 1G17 won't.

    With regards to the LSF for I2C, you certainly could given that it isn't LSF0101 since it's just a 1 channel. But i'm assuming you were hoping to put the voltage translator for this clock and your I2C all on the same LSF chip, which probably wouldn't be necessary right now. If you have the TXS already and you go with the AUC for the clock, I don't see a need to trade them out.

    Thanks,
    Rami Mooti

  • Hi Rami

    Thanks for your recommendations. Given the options I think I will stick with LSF0102 because typical rise/fall time for LSF0102 at CL=15pf is 0.3/0.4ns, whereas for AUC1G125 it is 1ns

    If I provide 3.3V input to AUC1G125 when its Vcc =1.8V, will that not overstress the device, even though input can support up to 3.6V?

    Thanks for your help with this matter

    Kind regards

    Navin

  • Navin,

    The LSF could be a good solution but I would still push for the AUC1G125. Applying 3.3V when the Vcc is 1.8V isn't a problem. The input pins are over voltage tolerant so regardless of the Vcc level, the input voltages will be able to handle up to 3.6V. You can see that the recommended input voltage isn't referenced to VCC but rather it is listed as 3.6V.




    I believe the 0.3/0.4 ns you're seeing is the propagation delay, not the rise/fall time. I found this image in a different datasheet that makes it a bit more clear as to what each is referring to. The tplh is the propagation time from a low to high input while the tphl is the propagation from a high to low. This is not the actual rise/fall time. This is the timing delay between the input and output from the same spot (Usually VCC/2) on the signal between input and output. 





    Hope this helps,
    Rami

  • Hi Rami

    Thanks for the confirmation, I was looking at the wrong parameter. On the AUC1G125 datasheet page 5 it says recommended input transition rise/fall rate is 10ns/V if Vcc=1.8V, but the REFCLK signal rise/fall rate will be max 1ns/1.8V = 0.55ns/V. Will the AUC or LSF devices be able to cope with this rise/fall time? or will it slow down the output signal?

    Thanks

    Navin

  • Navin,

    I may have misunderstood your setup. From my understanding you're using an external clock that will be at 3.3V. You're aiming to down translate this to 1.8V to be fed into the REFCLK input of the SN65DS. The rising edge for the RECLK needs to be between 100ps and 1ns. It itself is just an input with no rise/fall time just limitations on what the rise/fall time should be. 
    The input transition rise/fall rate of 10ns/V you're speaking about would be the input coming into the AUC1G125 device. This would be the 3.3V clock source you have initially. Is the rise/fall time of that source exceeding the spec?

    Thanks,
    Rami 

  • Hi Rami

    Yes, I'm using an external clock running at 3.3V (lets call it REFCLK_3V3). REFCLK_3V3 must pass through the level translator and go to the input of the SN65DS. Therefore REFCLK_3V3 must have a rising edge between 0.1-1ns in order to meet the SN65DS spec. But I am concerned that the AUC device may not be able to cope with the fast rise time of REFCLK_3V3. As the input rise/fall rate of AUC is 10ns/V, and the 3.3V clock source rise time might be <0.55ns/V.

    In any case I am using both parts (AUC and LSF) in my circuit as seen in the related post (link), I will test both parts and remove the one that gives me worse performance.

    Thanks
    Navin

  • Navin, 
    Testing is a good way to confirm this. Since we have continued our dialogue on the other post regarding your testing, i'll close this thread out.
    Rami